Nellyw888/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb
Reinforcement Learning
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Verireason
Dataset and Model for paper: "VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation"
Note Come check our web page: https://nellyw8.github.io/VeriReason/ Please cite out paper if you find our work useful! https://arxiv.org/pdf/2505.11849
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Nellyw888/VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb
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Nellyw888/VeriReason-Qwen2.5-1.5b-RTLCoder-Verilog-GRPO-reasoning-tb
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Nellyw888/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb
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Nellyw888/RTL-Coder_small
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Nellyw888/VeriReason-RTL-Coder_7b_reasoning_tb
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Nellyw888/RTL-Coder_7b_reasoning_tb_combined
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Nellyw888/VeriReason-RTL-Coder_7b_reasoning_tb_simple
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VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation
Paper • 2505.11849 • Published • 2Note Please cite out paper if you find our work useful! @misc{wang2025verireasonreinforcementlearningtestbench, title={VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation}, author={Yiting Wang and Guoheng Sun and Wanghao Ye and Gang Qu and Ang Li}, year={2025}, eprint={2505.11849}, archivePrefix={arXiv}, primaryClass={cs.AI}, url={https://arxiv.org/abs/2505.11849}, }