Again

data/riscv_comprehensive_corpus/core-specs/extensions/vector-intrinsic-specification.pdf

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:148f31560335620da20330727a35184e90cfed635d32ef0055511995dc0c9c07
+size 8217551

data/riscv_comprehensive_corpus/core-specs/official/riscv-spec-privileged-v20250508.pdf

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:d0228bbecc76943aaa5685e381e0263a8c750d18b1b0c452b086b0ddd15a4955
+size 1372206

data/riscv_comprehensive_corpus/core-specs/official/riscv-spec-unprivileged-v20250508.pdf

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:cef2e63c08c6f82cf7acc9056a589954f5b1adf6f7dccaa38cd75278b093e984
+size 4643378

data/riscv_comprehensive_corpus/core-specs/profiles/rva23-profile.pdf

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:af3519cdbfa1b3f12db6389b0bb9bcae171bf24fffd0dcf51d195ef49aaa9cfc
+size 149681

data/riscv_comprehensive_corpus/core-specs/profiles/rvb23-profile.pdf

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:840332dda22c697dd722253bf4fccd7e15fa0c8a355be3c9d9ea6b7be0bf145a
+size 140067

data/riscv_comprehensive_corpus/core-specs/standards/riscv-abis-specification.pdf

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:a8d06bdcaa82a6a4567a1904dc27ef1ca1043ebaa1f523558c927a9d72bc23d9
+size 273939

data/riscv_comprehensive_corpus/core-specs/standards/riscv-debug-specification.pdf

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:ce2787b25233a6109c9bc767b2bc497798148b721390f72fb9b48ff0ed986fc8
+size 2495279

data/riscv_comprehensive_corpus/core-specs/standards/riscv-sbi-specification.pdf

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:ae407195083fff6d71c33d72a9c32cea4cdf08ca054afc6907550b1cda218e5e
+size 464914

data/riscv_comprehensive_corpus/implementation/debug/efficient-trace-riscv.pdf

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:dba07d8671a80ad483805f9a72d6fb419a9f31f73ba6bd8d83ede70acb48d0cc
+size 802444

data/riscv_comprehensive_corpus/implementation/debug/n-trace-nexus.pdf

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:a87c90a3b6282cfa0d0b322c76cc55e02ab4de1349c1d7920a9dcf862e45e7f6
+size 562783

data/riscv_comprehensive_corpus/implementation/debug/trace-connectors.pdf

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:f7d0281f0de748a50f55dc2c2afefbb6578453b5f7bee5c153defdb57f330324
+size 141033

data/riscv_comprehensive_corpus/implementation/debug/trace-control-interface.pdf

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:ff623e2dd97af70768d93c0a8414740d31ab9d2cee2cbea1cc427fb79098b889
+size 547648

data/riscv_comprehensive_corpus/implementation/firmware/uefi-protocol-specification.pdf

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:0ebf3e21024d3e5a7e2e179712ecf384c4b9d6dcd5eb342539903d9d8b371af0
+size 158934

data/riscv_comprehensive_corpus/implementation/soc/server-soc-specification.pdf

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:6964639f1d0d7c39fa9bde93a1425b008321b28787340ad4db9791f6ae63e5f3
+size 391161

data/riscv_comprehensive_corpus/implementation/system/advanced-interrupt-architecture.pdf

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:9b9fa0d4c9ec45eaae02ef9af2680125b937dfe0b91891497c69421ce52fdbc5
+size 529223

data/riscv_comprehensive_corpus/implementation/system/iommu-architecture.pdf

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:aab9bdfa0fa7770ad0910a39d80d9ea65c37deacda498e9946af319e32450cc4
+size 1034129

data/riscv_comprehensive_corpus/implementation/system/platform-interrupt-controller.pdf

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:82644c7701601baad8abe8b8c194a6aa89d0c1c26029f590f20818e319ccb21a
+size 545211

data/riscv_comprehensive_corpus/implementation/system/semihosting-specification.pdf

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:b6ea9bc0845c207a9ab8e01f02e184202f4a7dbb516b09eade9b589bcbba0a5d
+size 137522

data/riscv_comprehensive_corpus/metadata/download-log.json

@@ -0,0 +1,668 @@
+{
+  "collection_date": "2025-07-14T11:36:43.530837",
+  "statistics": {
+    "downloaded": 0,
+    "skipped": 55,
+    "failed": 0,
+    "total_size_mb": 0.0
+  },
+  "downloads": [
+    {
+      "url": "https://drive.google.com/uc?export=download&id=1uviu1nH-tScFfgrovvFCrj7Omv8tFtkp",
+      "url_hash": "a76f15a9947a65bafb9facfe800446c5",
+      "local_path": "data/riscv_comprehensive_corpus/core-specs/official/riscv-spec-unprivileged-v20250508.pdf",
+      "title": "RISC-V Instruction Set Manual Volume I: Unprivileged ISA (May 2025)",
+      "size_mb": 4.43,
+      "download_date": "2025-07-14T11:28:11.657251",
+      "status": "success"
+    },
+    {
+      "url": "https://drive.google.com/uc?export=download&id=17GeetSnT5wW3xNuAHI95-SI1gPGd5sJ_",
+      "url_hash": "3af473107bc37baf2d874cbc7732fe8e",
+      "local_path": "data/riscv_comprehensive_corpus/core-specs/official/riscv-spec-privileged-v20250508.pdf",
+      "title": "RISC-V Instruction Set Manual Volume II: Privileged Architecture (May 2025)",
+      "size_mb": 1.31,
+      "download_date": "2025-07-14T11:28:15.321163",
+      "status": "success"
+    },
+    {
+      "url": "https://drive.google.com/uc?export=download&id=1Ja_Tpp_5Me583CGVD-BIZMlgGBnlKU4R",
+      "url_hash": "60da222424ea3fd303af0ddcd554a543",
+      "local_path": "data/riscv_comprehensive_corpus/core-specs/standards/riscv-abis-specification.pdf",
+      "title": "RISC-V ABIs Specification",
+      "size_mb": 0.26,
+      "download_date": "2025-07-14T11:28:17.924867",
+      "status": "success"
+    },
+    {
+      "url": "https://drive.google.com/uc?export=download&id=1h_f9NgB_8m2fS6uCnKP1Oho-3x1MpBEl",
+      "url_hash": "1193eefb87a00b513d53b3e195fdc544",
+      "local_path": "data/riscv_comprehensive_corpus/core-specs/standards/riscv-debug-specification.pdf",
+      "title": "RISC-V Debug Specification",
+      "size_mb": 2.38,
+      "download_date": "2025-07-14T11:28:21.447511",
+      "status": "success"
+    },
+    {
+      "url": "https://drive.google.com/uc?export=download&id=1U2kwjqxXgDONXk_-ZDTYzvsV-F_8ylEH",
+      "url_hash": "feb5dfcf0659830c3e5c0f81c262b4de",
+      "local_path": "data/riscv_comprehensive_corpus/core-specs/standards/riscv-sbi-specification.pdf",
+      "title": "RISC-V Supervisor Binary Interface Specification",
+      "size_mb": 0.44,
+      "download_date": "2025-07-14T11:28:24.691606",
+      "status": "success"
+    },
+    {
+      "url": "https://drive.google.com/uc?export=download&id=12QKRm92cLcEk8-5J9NI91m0fAQOxqNAq",
+      "url_hash": "1f0395a95fb8db25599620e838b25408",
+      "local_path": "data/riscv_comprehensive_corpus/core-specs/profiles/rva23-profile.pdf",
+      "title": "RVA23 Profile Specification",
+      "size_mb": 0.14,
+      "download_date": "2025-07-14T11:28:27.662272",
+      "status": "success"
+    },
+    {
+      "url": "https://drive.google.com/uc?export=download&id=1pBQAeTasG6smBxZc_zLkQU1GPA4Zngo7",
+      "url_hash": "61e89b116ce3a993b460fc9e6f6cd217",
+      "local_path": "data/riscv_comprehensive_corpus/core-specs/profiles/rvb23-profile.pdf",
+      "title": "RVB23 Profile Specification",
+      "size_mb": 0.13,
+      "download_date": "2025-07-14T11:28:30.220705",
+      "status": "success"
+    },
+    {
+      "url": "https://drive.google.com/uc?export=download&id=1RTZi2iOLKzqaX95JCCnzwOm7iCIN3JEq",
+      "url_hash": "486196ed953dd51a1706fe6bb60852a1",
+      "local_path": "data/riscv_comprehensive_corpus/core-specs/extensions/vector-intrinsic-specification.pdf",
+      "title": "RISC-V Vector C Intrinsic Specification",
+      "size_mb": 7.84,
+      "download_date": "2025-07-14T11:28:46.582783",
+      "status": "success"
+    },
+    {
+      "url": "https://drive.google.com/uc?export=download&id=1iijHsZB7YXW0A2HuuzHo5QTZSKrO_KbW",
+      "url_hash": "95b0e9e9d2d0aa7cdfc63ce84f32a600",
+      "local_path": "data/riscv_comprehensive_corpus/implementation/debug/efficient-trace-riscv.pdf",
+      "title": "Efficient Trace for RISC-V Specification",
+      "size_mb": 0.77,
+      "download_date": "2025-07-14T11:28:52.458516",
+      "status": "success"
+    },
+    {
+      "url": "https://drive.google.com/uc?export=download&id=16life2Y5u7Plebbl4v1fFM1-NK-KHw0Y",
+      "url_hash": "5959349a62c42fd9109165ad5f137e7d",
+      "local_path": "data/riscv_comprehensive_corpus/implementation/system/advanced-interrupt-architecture.pdf",
+      "title": "RISC-V Advanced Interrupt Architecture",
+      "size_mb": 0.5,
+      "download_date": "2025-07-14T11:28:56.420857",
+      "status": "success"
+    },
+    {
+      "url": "https://drive.google.com/uc?export=download&id=1at94PNJl4v2eAsKIwKOsZWBxsVcY2U2F",
+      "url_hash": "90f977b5d1d75f0031a5009ba5b401e7",
+      "local_path": "data/riscv_comprehensive_corpus/implementation/system/platform-interrupt-controller.pdf",
+      "title": "RISC-V Platform-Level Interrupt Controller Specification",
+      "size_mb": 0.52,
+      "download_date": "2025-07-14T11:28:58.995265",
+      "status": "success"
+    },
+    {
+      "url": "https://drive.google.com/uc?export=download&id=1kVapIJPXUUNFQv_yauCDgtWzMvpgh6C2",
+      "url_hash": "a433c779d4f0ccd7a0ab503f5f051530",
+      "local_path": "data/riscv_comprehensive_corpus/implementation/system/iommu-architecture.pdf",
+      "title": "RISC-V IOMMU Architecture Specification",
+      "size_mb": 0.99,
+      "download_date": "2025-07-14T11:29:02.191780",
+      "status": "success"
+    },
+    {
+      "url": "https://drive.google.com/uc?export=download&id=1KjewRE0NltEmbKOz7YlgOsTF51lZ6aPL",
+      "url_hash": "649df8174dbf6c343c4b764f1c19bfc0",
+      "local_path": "data/riscv_comprehensive_corpus/implementation/soc/server-soc-specification.pdf",
+      "title": "RISC-V Server SOC Specification",
+      "size_mb": 0.37,
+      "download_date": "2025-07-14T11:29:04.749069",
+      "status": "success"
+    },
+    {
+      "url": "https://drive.google.com/uc?export=download&id=1qu74D4_EmjGmc03qzfQ7Pf4g6m0fOtcD",
+      "url_hash": "e6da1120a47b87ca10d3831c80e330aa",
+      "local_path": "data/riscv_comprehensive_corpus/implementation/system/semihosting-specification.pdf",
+      "title": "RISC-V Semihosting Specification",
+      "size_mb": 0.13,
+      "download_date": "2025-07-14T11:29:07.470198",
+      "status": "success"
+    },
+    {
+      "url": "https://drive.google.com/uc?export=download&id=1rbQDRkoeJyqTKTI6tTCKw8zmh7T9dLUZ",
+      "url_hash": "bc12474970de366030b48cdfc2316b10",
+      "local_path": "data/riscv_comprehensive_corpus/implementation/firmware/uefi-protocol-specification.pdf",
+      "title": "RISC-V UEFI Protocol Specification",
+      "size_mb": 0.15,
+      "download_date": "2025-07-14T11:29:10.048446",
+      "status": "success"
+    },
+    {
+      "url": "https://drive.google.com/uc?export=download&id=1UXFptcTjd5akPhKRtn0onBC6t53O61qU",
+      "url_hash": "c809b8b450c74744298f04e9e7e1554a",
+      "local_path": "data/riscv_comprehensive_corpus/implementation/debug/n-trace-nexus.pdf",
+      "title": "RISC-V N-Trace (Nexus-based Trace) Specification",
+      "size_mb": 0.54,
+      "download_date": "2025-07-14T11:29:13.124325",
+      "status": "success"
+    },
+    {
+      "url": "https://drive.google.com/uc?export=download&id=1ZQvU1WNamY5EHGum4yP1z-WmPrcxH2b8",
+      "url_hash": "6da571c2156a41d969554e5205d80b8c",
+      "local_path": "data/riscv_comprehensive_corpus/implementation/debug/trace-control-interface.pdf",
+      "title": "RISC-V Trace Control Interface Specification",
+      "size_mb": 0.52,
+      "download_date": "2025-07-14T11:29:15.931701",
+      "status": "success"
+    },
+    {
+      "url": "https://drive.google.com/uc?export=download&id=1SMypv0CUL338L-sURMyJuO60WZ7oDi9V",
+      "url_hash": "fc0e1d65c61852153147627217c5569f",
+      "local_path": "data/riscv_comprehensive_corpus/implementation/debug/trace-connectors.pdf",
+      "title": "RISC-V Trace Connectors Specification",
+      "size_mb": 0.13,
+      "download_date": "2025-07-14T11:29:18.445497",
+      "status": "success"
+    },
+    {
+      "url": "https://drive.google.com/uc?export=download&id=1XSKqg6MXEmRdpdUYLj-Q03kZD6TDQhtu",
+      "url_hash": "322b2b80b73c0d440ff195aa32a995e5",
+      "local_path": "data/riscv_comprehensive_corpus/research/system/qos-register-interface.pdf",
+      "title": "RISC-V Capacity and Bandwidth QoS Register Interface",
+      "size_mb": 0.29,
+      "download_date": "2025-07-14T11:29:23.608174",
+      "status": "success"
+    },
+    {
+      "url": "https://drive.google.com/uc?export=download&id=19gMRFbWDrfDZKyqoO3iFkySPvKpxm26a",
+      "url_hash": "e75681f13ba7e37c714a2a0e309fb344",
+      "local_path": "data/riscv_comprehensive_corpus/research/system/reri-architecture.pdf",
+      "title": "RISC-V RERI Architecture Specification",
+      "size_mb": 0.18,
+      "download_date": "2025-07-14T11:29:26.231700",
+      "status": "success"
+    },
+    {
+      "url": "https://drive.google.com/uc?export=download&id=1XzlA0LE4N5_47wJXsU3aqyD69pHGvdcL",
+      "url_hash": "8be5620d4d38e1b6413016137d396581",
+      "local_path": "data/riscv_comprehensive_corpus/research/system/functional-fixed-hardware.pdf",
+      "title": "RISC-V Functional Fixed Hardware Specification",
+      "size_mb": 0.09,
+      "download_date": "2025-07-14T11:29:28.493463",
+      "status": "success"
+    },
+    {
+      "url": "https://drive.google.com/uc?export=download&id=1sxQ3iQ1l5Jgq9tukvGMnucRUvY16s8zN",
+      "url_hash": "94b50cdd97883b8b0d22e17694aa5af8",
+      "local_path": "data/riscv_comprehensive_corpus/research/system/io-mapping-table.pdf",
+      "title": "RISC-V IO Mapping Table Specification",
+      "size_mb": 0.13,
+      "download_date": "2025-07-14T11:29:31.989064",
+      "status": "success"
+    },
+    {
+      "url": "https://drive.google.com/uc?export=download&id=1R-_koXIpdb9_qW6jpz74TSnNXOfJGhfn",
+      "url_hash": "f39d871e5c1d9656dceae80a6c4124c4",
+      "local_path": "data/riscv_comprehensive_corpus/research/debug/trace-encapsulation.pdf",
+      "title": "Unformatted Trace & Diagnostic Data Packet Encapsulation for RISC-V",
+      "size_mb": 0.1,
+      "download_date": "2025-07-14T11:29:34.369425",
+      "status": "success"
+    },
+    {
+      "url": "http://arxiv.org/pdf/1908.11648v3",
+      "url_hash": "61ff1358ca6df5bcc638f2173a559bf7",
+      "local_path": "data/riscv_comprehensive_corpus/research/papers/security-studies/1908.11648v3.pdf",
+      "title": "Porting of eChronos RTOS on RISC-V Architecture",
+      "size_mb": 0.24,
+      "download_date": "2025-07-14T11:32:33.962362",
+      "status": "success"
+    },
+    {
+      "url": "http://arxiv.org/pdf/1607.02318v1",
+      "url_hash": "d15febad88cec6115fd3c3939df1fb1e",
+      "local_path": "data/riscv_comprehensive_corpus/research/papers/performance-analysis/1607.02318v1.pdf",
+      "title": "The Renewed Case for the Reduced Instruction Set Computer: Avoiding ISA Bloat with Macro-Op Fusion for RISC-V",
+      "size_mb": 0.43,
+      "download_date": "2025-07-14T11:32:35.276791",
+      "status": "success"
+    },
+    {
+      "url": "http://arxiv.org/pdf/2305.09266v1",
+      "url_hash": "298170ad0e2b8432fff62098bf5c3243",
+      "local_path": "data/riscv_comprehensive_corpus/research/papers/performance-analysis/2305.09266v1.pdf",
+      "title": "Case Study for Running Memory-Bound Kernels on RISC-V CPUs",
+      "size_mb": 0.87,
+      "download_date": "2025-07-14T11:32:37.066431",
+      "status": "success"
+    },
+    {
+      "url": "http://arxiv.org/pdf/2305.00584v2",
+      "url_hash": "a292dcc81b8be0dae43fb7947aacf5cd",
+      "local_path": "data/riscv_comprehensive_corpus/research/papers/performance-analysis/2305.00584v2.pdf",
+      "title": "MAMBO-V: Dynamic Side-Channel Leakage Analysis on RISC-V",
+      "size_mb": 0.55,
+      "download_date": "2025-07-14T11:32:38.813807",
+      "status": "success"
+    },
+    {
+      "url": "http://arxiv.org/pdf/2506.08653v1",
+      "url_hash": "c8a5148d7b91012dee22379f5cb83426",
+      "local_path": "data/riscv_comprehensive_corpus/research/papers/performance-analysis/2506.08653v1.pdf",
+      "title": "Parallel FFTW on RISC-V: A Comparative Study including OpenMP, MPI, and HPX",
+      "size_mb": 0.45,
+      "download_date": "2025-07-14T11:32:39.852411",
+      "status": "success"
+    },
+    {
+      "url": "http://arxiv.org/pdf/2312.01455v1",
+      "url_hash": "f2baaf514349e6ba187fdad278b1e393",
+      "local_path": "data/riscv_comprehensive_corpus/research/papers/architecture-studies/2312.01455v1.pdf",
+      "title": "32-Bit RISC-V CPU Core on Logisim",
+      "size_mb": 1.76,
+      "download_date": "2025-07-14T11:32:42.182148",
+      "status": "success"
+    },
+    {
+      "url": "http://arxiv.org/pdf/2107.04175v1",
+      "url_hash": "231308bb4678c23ee296cf72671021cf",
+      "local_path": "data/riscv_comprehensive_corpus/research/papers/security-studies/2107.04175v1.pdf",
+      "title": "A Survey on RISC-V Security: Hardware and Architecture",
+      "size_mb": 2.24,
+      "download_date": "2025-07-14T11:32:44.406367",
+      "status": "success"
+    },
+    {
+      "url": "http://arxiv.org/pdf/2507.01457v1",
+      "url_hash": "dba6b45beebf80224931116aaf9aa422",
+      "local_path": "data/riscv_comprehensive_corpus/research/papers/performance-analysis/2507.01457v1.pdf",
+      "title": "Tensor Program Optimization for the RISC-V Vector Extension Using Probabilistic Programs",
+      "size_mb": 0.39,
+      "download_date": "2025-07-14T11:32:45.487551",
+      "status": "success"
+    },
+    {
+      "url": "http://arxiv.org/pdf/2409.00661v1",
+      "url_hash": "485f3302c41e679131e5d3aa9986e9c5",
+      "local_path": "data/riscv_comprehensive_corpus/research/papers/performance-analysis/2409.00661v1.pdf",
+      "title": "Research on LLM Acceleration Using the High-Performance RISC-V Processor \"Xiangshan\" (Nanhu Version) Based on the Open-Source Matrix Instruction Set Extension (Vector Dot Product)",
+      "size_mb": 0.71,
+      "download_date": "2025-07-14T11:32:46.533084",
+      "status": "success"
+    },
+    {
+      "url": "http://arxiv.org/pdf/2010.16171v1",
+      "url_hash": "626a1507259cf9127b0687b2352a88b3",
+      "local_path": "data/riscv_comprehensive_corpus/research/papers/performance-analysis/2010.16171v1.pdf",
+      "title": "RVCoreP-32IM: An effective architecture to implement mul/div instructions for five stage RISC-V soft processors",
+      "size_mb": 0.3,
+      "download_date": "2025-07-14T11:32:47.765571",
+      "status": "success"
+    },
+    {
+      "url": "http://arxiv.org/pdf/2407.00026v2",
+      "url_hash": "96f52e75ca06323df60380d903289575",
+      "local_path": "data/riscv_comprehensive_corpus/research/papers/performance-analysis/2407.00026v2.pdf",
+      "title": "Preparing for HPC on RISC-V: Examining Vectorization and Distributed Performance of an Astrophyiscs Application with HPX and Kokkos",
+      "size_mb": 1.46,
+      "download_date": "2025-07-14T11:32:48.826337",
+      "status": "success"
+    },
+    {
+      "url": "http://arxiv.org/pdf/2502.13839v2",
+      "url_hash": "ca09555703c2aaffe492d2bb593894e6",
+      "local_path": "data/riscv_comprehensive_corpus/research/papers/performance-analysis/2502.13839v2.pdf",
+      "title": "Performance optimization of BLAS algorithms with band matrices for RISC-V processors",
+      "size_mb": 0.76,
+      "download_date": "2025-07-14T11:32:49.868320",
+      "status": "success"
+    },
+    {
+      "url": "http://arxiv.org/pdf/2002.03568v1",
+      "url_hash": "608057416de35d9552b8047a86d2d130",
+      "local_path": "data/riscv_comprehensive_corpus/research/papers/performance-analysis/2002.03568v1.pdf",
+      "title": "RVCoreP : An optimized RISC-V soft processor of five-stage pipelining",
+      "size_mb": 0.23,
+      "download_date": "2025-07-14T11:32:51.080942",
+      "status": "success"
+    },
+    {
+      "url": "http://arxiv.org/pdf/2505.04567v2",
+      "url_hash": "01be8a431d59ba0ee5268b0b66ed2f0f",
+      "local_path": "data/riscv_comprehensive_corpus/research/papers/performance-analysis/2505.04567v2.pdf",
+      "title": "Flexing RISC-V Instruction Subset Processors (RISPs) to Extreme Edge",
+      "size_mb": 2.52,
+      "download_date": "2025-07-14T11:32:52.155913",
+      "status": "success"
+    },
+    {
+      "url": "http://arxiv.org/pdf/2309.00381v2",
+      "url_hash": "2edf6484fabdd1212840d57480338a4f",
+      "local_path": "data/riscv_comprehensive_corpus/research/papers/performance-analysis/2309.00381v2.pdf",
+      "title": "Is RISC-V ready for HPC prime-time: Evaluating the 64-core Sophon SG2042 RISC-V CPU",
+      "size_mb": 0.25,
+      "download_date": "2025-07-14T11:32:53.381514",
+      "status": "success"
+    },
+    {
+      "url": "http://arxiv.org/pdf/2211.10299v2",
+      "url_hash": "a433306bdd6a7bae8449e9d791b4359a",
+      "local_path": "data/riscv_comprehensive_corpus/research/papers/security-studies/2211.10299v2.pdf",
+      "title": "Trusted Hart for Mobile RISC-V Security",
+      "size_mb": 0.67,
+      "download_date": "2025-07-14T11:34:57.363312",
+      "status": "success"
+    },
+    {
+      "url": "http://arxiv.org/pdf/2405.11062v1",
+      "url_hash": "de800d118fc622dcab0643a287b974e4",
+      "local_path": "data/riscv_comprehensive_corpus/research/papers/performance-analysis/2405.11062v1.pdf",
+      "title": "Vectorization of Gradient Boosting of Decision Trees Prediction in the CatBoost Library for RISC-V Processors",
+      "size_mb": 1.09,
+      "download_date": "2025-07-14T11:34:59.480836",
+      "status": "success"
+    },
+    {
+      "url": "http://arxiv.org/pdf/2311.05284v1",
+      "url_hash": "bb43225ff09cc10ed84ba60e9673fb4e",
+      "local_path": "data/riscv_comprehensive_corpus/research/papers/performance-analysis/2311.05284v1.pdf",
+      "title": "Challenges and Opportunities in the Co-design of Convolutions and RISC-V Vector Processors",
+      "size_mb": 0.59,
+      "download_date": "2025-07-14T11:35:00.732361",
+      "status": "success"
+    },
+    {
+      "url": "http://arxiv.org/pdf/2504.05284v1",
+      "url_hash": "eb39ff56846bf48201f40a2d701b1a8d",
+      "local_path": "data/riscv_comprehensive_corpus/research/papers/performance-analysis/2504.05284v1.pdf",
+      "title": "FERIVer: An FPGA-assisted Emulated Framework for RTL Verification of RISC-V Processors",
+      "size_mb": 0.73,
+      "download_date": "2025-07-14T11:35:01.815091",
+      "status": "success"
+    },
+    {
+      "url": "http://arxiv.org/pdf/2407.14274v2",
+      "url_hash": "df5e30aead35410d3dfd700f430823b0",
+      "local_path": "data/riscv_comprehensive_corpus/research/papers/performance-analysis/2407.14274v2.pdf",
+      "title": "Mixed-precision Neural Networks on RISC-V Cores: ISA extensions for Multi-Pumped Soft SIMD Operations",
+      "size_mb": 2.82,
+      "download_date": "2025-07-14T11:35:03.962701",
+      "status": "success"
+    },
+    {
+      "url": "http://arxiv.org/pdf/2002.03576v2",
+      "url_hash": "9b324a9f8326d02bfabe3e137f9330e0",
+      "local_path": "data/riscv_comprehensive_corpus/research/papers/architecture-studies/2002.03576v2.pdf",
+      "title": "A portable and Linux capable RISC-V computer system in Verilog HDL",
+      "size_mb": 0.26,
+      "download_date": "2025-07-14T11:35:05.234832",
+      "status": "success"
+    },
+    {
+      "url": "http://arxiv.org/pdf/1905.06825v1",
+      "url_hash": "82a3e89be59abb71e516d13c8f8835ae",
+      "local_path": "data/riscv_comprehensive_corpus/research/papers/performance-analysis/1905.06825v1.pdf",
+      "title": "Fast TLB Simulation for RISC-V Systems",
+      "size_mb": 0.62,
+      "download_date": "2025-07-14T11:35:06.592814",
+      "status": "success"
+    },
+    {
+      "url": "http://arxiv.org/pdf/2409.18835v1",
+      "url_hash": "66b00d9f9c0880ef5030f7801d5a6bdb",
+      "local_path": "data/riscv_comprehensive_corpus/research/papers/performance-analysis/2409.18835v1.pdf",
+      "title": "Accelerating stencils on the Tenstorrent Grayskull RISC-V accelerator",
+      "size_mb": 0.29,
+      "download_date": "2025-07-14T11:35:07.715313",
+      "status": "success"
+    },
+    {
+      "url": "http://arxiv.org/pdf/2407.13326v1",
+      "url_hash": "af891ab97af5d6367f86369efd275f05",
+      "local_path": "data/riscv_comprehensive_corpus/research/papers/performance-analysis/2407.13326v1.pdf",
+      "title": "RISC-V RVV efficiency for ANN algorithms",
+      "size_mb": 0.57,
+      "download_date": "2025-07-14T11:35:08.749585",
+      "status": "success"
+    },
+    {
+      "url": "http://arxiv.org/pdf/2412.05286v1",
+      "url_hash": "6e6d33383039f95f363148fefb2b5e2c",
+      "local_path": "data/riscv_comprehensive_corpus/research/papers/performance-analysis/2412.05286v1.pdf",
+      "title": "RISC-V Word-Size Modular Instructions for Residue Number Systems",
+      "size_mb": 0.59,
+      "download_date": "2025-07-14T11:35:09.779620",
+      "status": "success"
+    },
+    {
+      "url": "http://arxiv.org/pdf/2011.11246v1",
+      "url_hash": "709fe2732fb0b9e83032ee41b0739e6a",
+      "local_path": "data/riscv_comprehensive_corpus/research/papers/performance-analysis/2011.11246v1.pdf",
+      "title": "RVCoreP-32IC: A high-performance RISC-V soft processor with an efficient fetch unit supporting the compressed instructions",
+      "size_mb": 0.49,
+      "download_date": "2025-07-14T11:35:10.913936",
+      "status": "success"
+    },
+    {
+      "url": "http://arxiv.org/pdf/2504.03722v1",
+      "url_hash": "8fc864d449f0faf2491b7e8365c25ff8",
+      "local_path": "data/riscv_comprehensive_corpus/research/papers/architecture-studies/2504.03722v1.pdf",
+      "title": "WebRISC-V: A 64-bit RISC-V Pipeline Simulator for Computer Architecture Classes",
+      "size_mb": 0.27,
+      "download_date": "2025-07-14T11:35:12.029619",
+      "status": "success"
+    },
+    {
+      "url": "http://arxiv.org/pdf/2506.06693v1",
+      "url_hash": "bc3473f949b94a3dbc1b81d262c65cf8",
+      "local_path": "data/riscv_comprehensive_corpus/research/papers/performance-analysis/2506.06693v1.pdf",
+      "title": "Design and Implementation of a RISC-V SoC with Custom DSP Accelerators for Edge Computing",
+      "size_mb": 0.3,
+      "download_date": "2025-07-14T11:35:13.062960",
+      "status": "success"
+    },
+    {
+      "url": "http://arxiv.org/pdf/2501.10189v1",
+      "url_hash": "1daad10446c096d3c88e30dda7fef518",
+      "local_path": "data/riscv_comprehensive_corpus/research/papers/performance-analysis/2501.10189v1.pdf",
+      "title": "Optimizing Structured-Sparse Matrix Multiplication in RISC-V Vector Processors",
+      "size_mb": 13.51,
+      "download_date": "2025-07-14T11:35:14.399525",
+      "status": "success"
+    },
+    {
+      "url": "http://arxiv.org/pdf/2112.11767v1",
+      "url_hash": "112763c4676bbefa79c04b5cbca5214f",
+      "local_path": "data/riscv_comprehensive_corpus/research/papers/performance-analysis/2112.11767v1.pdf",
+      "title": "Supporting RISC-V Performance Counters through Performance analysis tools for Linux (Perf)",
+      "size_mb": 0.58,
+      "download_date": "2025-07-14T11:35:15.705540",
+      "status": "success"
+    },
+    {
+      "url": "http://arxiv.org/pdf/2304.10319v1",
+      "url_hash": "d6e52b1061a1934a99e50dae4b6a70db",
+      "local_path": "data/riscv_comprehensive_corpus/research/papers/performance-analysis/2304.10319v1.pdf",
+      "title": "Test-driving RISC-V Vector hardware for HPC",
+      "size_mb": 0.36,
+      "download_date": "2025-07-14T11:35:17.178889",
+      "status": "success"
+    },
+    {
+      "url": "http://arxiv.org/pdf/2411.12444v2",
+      "url_hash": "3d40d48bd0ebd0433455cc5ea72c1438",
+      "local_path": "data/riscv_comprehensive_corpus/research/papers/performance-analysis/2411.12444v2.pdf",
+      "title": "Advancing Cloud Computing Capabilities on gem5 by Implementing the RISC-V Hypervisor Extension",
+      "size_mb": 0.54,
+      "download_date": "2025-07-14T11:35:18.296659",
+      "status": "success"
+    },
+    {
+      "url": "http://arxiv.org/pdf/2206.08639v1",
+      "url_hash": "502eeb042bc378e7ea04d0a556e04666",
+      "local_path": "data/riscv_comprehensive_corpus/research/papers/architecture-studies/2206.08639v1.pdf",
+      "title": "Experimental evaluation of neutron-induced errors on a multicore RISC-V platform",
+      "size_mb": 0.74,
+      "download_date": "2025-07-14T11:35:19.682946",
+      "status": "success"
+    },
+    {
+      "url": "http://arxiv.org/pdf/2211.16212v1",
+      "url_hash": "4cd164cb047527552618197f96230d03",
+      "local_path": "data/riscv_comprehensive_corpus/research/papers/security-studies/2211.16212v1.pdf",
+      "title": "Control-Flow Integrity at RISC: Attacking RISC-V by Jump-Oriented Programming",
+      "size_mb": 0.61,
+      "download_date": "2025-07-14T11:35:21.463652",
+      "status": "success"
+    },
+    {
+      "url": "http://arxiv.org/pdf/2010.10119v1",
+      "url_hash": "106372672c6be16fbe1b4f181f7c1d9e",
+      "local_path": "data/riscv_comprehensive_corpus/research/papers/benchmarking/2010.10119v1.pdf",
+      "title": "A RISC-V SystemC-TLM simulator",
+      "size_mb": 0.64,
+      "download_date": "2025-07-14T11:35:23.027609",
+      "status": "success"
+    },
+    {
+      "url": "http://arxiv.org/pdf/2502.10194v1",
+      "url_hash": "d2a79006991169ac0b12c347f6162d0e",
+      "local_path": "data/riscv_comprehensive_corpus/research/papers/security-studies/2502.10194v1.pdf",
+      "title": "Translating Common Security Assertions Across Processor Designs: A RISC-V Case Study",
+      "size_mb": 0.69,
+      "download_date": "2025-07-14T11:35:24.068830",
+      "status": "success"
+    },
+    {
+      "url": "http://arxiv.org/pdf/2007.14995v1",
+      "url_hash": "d316ffd5f6dbd08dbe250eee4ea92b85",
+      "local_path": "data/riscv_comprehensive_corpus/research/papers/security-studies/2007.14995v1.pdf",
+      "title": "Return-Oriented Programming in RISC-V",
+      "size_mb": 0.12,
+      "download_date": "2025-07-14T11:35:25.366380",
+      "status": "success"
+    },
+    {
+      "url": "http://arxiv.org/pdf/2206.01901v1",
+      "url_hash": "44ec69c152af386976f785bdf7994c5c",
+      "local_path": "data/riscv_comprehensive_corpus/research/papers/architecture-studies/2206.01901v1.pdf",
+      "title": "Enabling Heterogeneous, Multicore SoC Research with RISC-V and ESP",
+      "size_mb": 0.97,
+      "download_date": "2025-07-14T11:35:26.994432",
+      "status": "success"
+    },
+    {
+      "url": "http://arxiv.org/pdf/2505.07112v2",
+      "url_hash": "c11e5d6f071160b678c43a466bb5c037",
+      "local_path": "data/riscv_comprehensive_corpus/research/papers/performance-analysis/2505.07112v2.pdf",
+      "title": "Efficient Implementation of RISC-V Vector Permutation Instructions",
+      "size_mb": 4.57,
+      "download_date": "2025-07-14T11:35:29.668866",
+      "status": "success"
+    },
+    {
+      "url": "http://arxiv.org/pdf/2106.08877v1",
+      "url_hash": "f5ef120e3a6ec17a3349b5eab425fd7e",
+      "local_path": "data/riscv_comprehensive_corpus/research/papers/security-studies/2106.08877v1.pdf",
+      "title": "Side-Channel Attacks on RISC-V Processors: Current Progress, Challenges, and Opportunities",
+      "size_mb": 1.04,
+      "download_date": "2025-07-14T11:35:31.367353",
+      "status": "success"
+    },
+    {
+      "url": "http://arxiv.org/pdf/2505.19096v1",
+      "url_hash": "b6faac45b8372c7a8098ad7fe9efd15d",
+      "local_path": "data/riscv_comprehensive_corpus/research/papers/architecture-studies/2505.19096v1.pdf",
+      "title": "Enable Lightweight and Precision-Scalable Posit/IEEE-754 Arithmetic in RISC-V Cores for Transprecision Computing",
+      "size_mb": 0.53,
+      "download_date": "2025-07-14T11:35:32.420545",
+      "status": "success"
+    },
+    {
+      "url": "http://arxiv.org/pdf/2304.12309v1",
+      "url_hash": "51b5b12912be2ec9eb8a1e0380a6e56a",
+      "local_path": "data/riscv_comprehensive_corpus/research/papers/performance-analysis/2304.12309v1.pdf",
+      "title": "Optimized Real-Time Assembly in a RISC Simulator",
+      "size_mb": 0.59,
+      "download_date": "2025-07-14T11:35:33.451554",
+      "status": "success"
+    },
+    {
+      "url": "http://arxiv.org/pdf/2505.10217v1",
+      "url_hash": "3e4ef5443867481932097176fb32c70a",
+      "local_path": "data/riscv_comprehensive_corpus/research/papers/architecture-studies/2505.10217v1.pdf",
+      "title": "Enabling Syscall Intercept for RISC-V",
+      "size_mb": 0.45,
+      "download_date": "2025-07-14T11:35:34.870448",
+      "status": "success"
+    },
+    {
+      "url": "http://arxiv.org/pdf/2106.07456v1",
+      "url_hash": "eadad3175aec601440c547653ab29229",
+      "local_path": "data/riscv_comprehensive_corpus/research/papers/performance-analysis/2106.07456v1.pdf",
+      "title": "Extending the RISC-V ISA for exploring advanced reconfigurable SIMD instructions",
+      "size_mb": 0.71,
+      "download_date": "2025-07-14T11:35:36.600068",
+      "status": "success"
+    },
+    {
+      "url": "http://arxiv.org/pdf/2503.04846v2",
+      "url_hash": "724379349c52a2f6463f1aab78709982",
+      "local_path": "data/riscv_comprehensive_corpus/research/papers/security-studies/2503.04846v2.pdf",
+      "title": "Honest to a Fault: Root-Causing Fault Attacks with Pre-Silicon RISC Pipeline Characterization",
+      "size_mb": 0.89,
+      "download_date": "2025-07-14T11:35:37.974499",
+      "status": "success"
+    },
+    {
+      "url": "http://arxiv.org/pdf/2304.10324v1",
+      "url_hash": "2d2a3808bc752a2bdf429badeb482b10",
+      "local_path": "data/riscv_comprehensive_corpus/research/papers/performance-analysis/2304.10324v1.pdf",
+      "title": "Backporting RISC-V Vector assembly",
+      "size_mb": 0.34,
+      "download_date": "2025-07-14T11:35:39.261281",
+      "status": "success"
+    },
+    {
+      "url": "http://arxiv.org/pdf/2307.12648v1",
+      "url_hash": "bdf4ed0cee1b222de93d840e6b03ea9e",
+      "local_path": "data/riscv_comprehensive_corpus/research/papers/security-studies/2307.12648v1.pdf",
+      "title": "Execution at RISC: Stealth JOP Attacks on RISC-V Applications",
+      "size_mb": 0.68,
+      "download_date": "2025-07-14T11:35:40.296636",
+      "status": "success"
+    },
+    {
+      "url": "http://arxiv.org/pdf/2405.15380v1",
+      "url_hash": "55e465948110fcb0754799bf21ea6f64",
+      "local_path": "data/riscv_comprehensive_corpus/research/papers/performance-analysis/2405.15380v1.pdf",
+      "title": "Full-stack evaluation of Machine Learning inference workloads for RISC-V systems",
+      "size_mb": 0.25,
+      "download_date": "2025-07-14T11:35:41.328477",
+      "status": "success"
+    },
+    {
+      "url": "http://arxiv.org/pdf/2103.08229v1",
+      "url_hash": "53ebf89c8f5e378434d89996c24a17c9",
+      "local_path": "data/riscv_comprehensive_corpus/research/papers/security-studies/2103.08229v1.pdf",
+      "title": "Return-Oriented Programming on RISC-V",
+      "size_mb": 0.77,
+      "download_date": "2025-07-14T11:35:42.766744",
+      "status": "success"
+    },
+    {
+      "url": "http://arxiv.org/pdf/2507.03773v1",
+      "url_hash": "65157935334f9c33dc4a8b7392dc7440",
+      "local_path": "data/riscv_comprehensive_corpus/research/papers/performance-analysis/2507.03773v1.pdf",
+      "title": "RVISmith: Fuzzing Compilers for RVV Intrinsics",
+      "size_mb": 1.04,
+      "download_date": "2025-07-14T11:35:44.286990",
+      "status": "success"
+    }
+  ]
+}

data/riscv_comprehensive_corpus/research/debug/trace-encapsulation.pdf

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:874bf26134a4560ab40b2ee7db957e623478db9498328f9112024dae64b223aa
+size 101752

data/riscv_comprehensive_corpus/research/papers/architecture-studies/2002.03576v2.pdf

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:1ac9f6c1333a8fa33fab74b578e9f46d1feeadc8381a86718379cdd24d17c8c5
+size 277836

data/riscv_comprehensive_corpus/research/papers/architecture-studies/2206.01901v1.pdf

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:e4adc65f54c9ad71d1ac82d0e31dbdb94d720f84ff1e76efadcf201ff38b5a7b
+size 1018087

data/riscv_comprehensive_corpus/research/papers/architecture-studies/2206.08639v1.pdf

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:17381f0472181452689680129da4405fc720d511246f9518b728a94999c91b5f
+size 772085

data/riscv_comprehensive_corpus/research/papers/architecture-studies/2312.01455v1.pdf

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:a4f58ad6300422e749a590715167aac6ec5bf3914c5d8fb3724d61b7b51e1c6d
+size 1847710

data/riscv_comprehensive_corpus/research/papers/architecture-studies/2504.03722v1.pdf

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:662cc12190ae887cb0605c476f74acd556296b0544d1d7e37edb7732dbe7a504
+size 278253

data/riscv_comprehensive_corpus/research/papers/architecture-studies/2505.10217v1.pdf

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:865ba3a1010ebbcadea506474d5ab982a59827265a95e04700ebc9c2dd1da6f8
+size 466834

data/riscv_comprehensive_corpus/research/papers/architecture-studies/2505.19096v1.pdf

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:f8f964803b0a4df90a8e4ac27a73410febe23cdf08b5cc00b810097c7710c957
+size 554313

data/riscv_comprehensive_corpus/research/papers/benchmarking/2010.10119v1.pdf

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:8d7e2e0014e5c7d0315e0235f05535b38480efb08bd8b4522d49682f4d41ae10
+size 672228

data/riscv_comprehensive_corpus/research/papers/performance-analysis/1607.02318v1.pdf

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:6bbd0a3578569c970c92f8f58300d4a1250afd36fa6aee6e0fc9699da819ad18
+size 447807

data/riscv_comprehensive_corpus/research/papers/performance-analysis/1905.06825v1.pdf

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:04a7624f7dabca52680b36bc1ec92f8d80cb50686a97a465ab3cb1b65c4d5b27
+size 644977

data/riscv_comprehensive_corpus/research/papers/performance-analysis/2002.03568v1.pdf

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:48c92fa7bd595f2ea7492f6b71371c52a0170810528c7f7abc3a451292bb2ae7
+size 243939

data/riscv_comprehensive_corpus/research/papers/performance-analysis/2010.16171v1.pdf

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:83b8680e39be76fb3d49b4130fbee5e618c155b6702f5c7da092f003f1a2c89e
+size 318842

data/riscv_comprehensive_corpus/research/papers/performance-analysis/2011.11246v1.pdf

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:20a468e4288501b2c1b302fd0bb8d03f07960200c6f4337c7cb73c09a4ab94a1
+size 516009

data/riscv_comprehensive_corpus/research/papers/performance-analysis/2106.07456v1.pdf

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:26f69c47411724c4b5836b674d6bccbe84722dd78d36964c10f9a8fc6f44e0e0
+size 740680

data/riscv_comprehensive_corpus/research/papers/performance-analysis/2112.11767v1.pdf

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:cfbba1d75808c396940fe2d3d20f022ea9d841c3557bb79811e0c721c278db09
+size 610524

data/riscv_comprehensive_corpus/research/papers/performance-analysis/2304.10319v1.pdf

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:eb766751513c05887e5033594261d87056f0d3f8263db652a2388b0bee8bcd99
+size 377111

data/riscv_comprehensive_corpus/research/papers/performance-analysis/2304.10324v1.pdf

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:c2907f22c0acff8a0e9d7e1c1ff5ec77ac6ba677acb71cab8c2bcbee403f778b
+size 356705

data/riscv_comprehensive_corpus/research/papers/performance-analysis/2304.12309v1.pdf

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:4704c1cd58de8de40df0f68fefc8ff55c6e71bf171d7e09b975aa238e10b7b69
+size 615222

data/riscv_comprehensive_corpus/research/papers/performance-analysis/2305.00584v2.pdf

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:6b8f20c49ecf9728989135f7d388024a6e7b22556776b14bd1354cdbd7549196
+size 575276

data/riscv_comprehensive_corpus/research/papers/performance-analysis/2305.09266v1.pdf

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:7fe214c1e7d7e399366d6cb55be4f2fe2e679a4c740a0a3c93cd7042d8ac67bf
+size 916028

data/riscv_comprehensive_corpus/research/papers/performance-analysis/2309.00381v2.pdf

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:da611a58dce496ddc86ec0a39200167603e92d30bf94d23cdcd7934886c7f811
+size 261533

data/riscv_comprehensive_corpus/research/papers/performance-analysis/2311.05284v1.pdf

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:d44fed1434e5dc18371636c822d09c68ed5b2b2209acfc42d166959670582c24
+size 614731

data/riscv_comprehensive_corpus/research/papers/performance-analysis/2405.11062v1.pdf

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:652680efdeceac6d299fd93a98dd4350b0908dcfd554d20db8960cc273007469
+size 1144795

data/riscv_comprehensive_corpus/research/papers/performance-analysis/2405.15380v1.pdf

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:a2461685a975a13b0fdb944a8e456d2e3eadfe30d818b3ce8e0ae259b9a570bb
+size 267146

data/riscv_comprehensive_corpus/research/papers/performance-analysis/2407.00026v2.pdf

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:91d5ab3e65bc046485b0212e14d5912a024a86539f91e5a4ca9c4fe2daef9d03
+size 1529622

data/riscv_comprehensive_corpus/research/papers/performance-analysis/2407.13326v1.pdf

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:1f605beb7d68c6882eb638d38c0492547858bf48b02444d1f3a72de2dc1ce548
+size 596978

data/riscv_comprehensive_corpus/research/papers/performance-analysis/2407.14274v2.pdf

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:24500d02e2ebbbd1bcb87a24ab18b32de5b1a29ae573c45a3772deb16cf2258b
+size 2959603

data/riscv_comprehensive_corpus/research/papers/performance-analysis/2409.00661v1.pdf

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:5a86cbf7e409b775e6b559e98d7d9305d851c45f92ca1f0a0e4cb5e731f52097
+size 741721

data/riscv_comprehensive_corpus/research/papers/performance-analysis/2409.18835v1.pdf

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:7c6b0af72652461fa9e406c3deabab1f49e787904b0b568358f001e0416dfadc
+size 302412

data/riscv_comprehensive_corpus/research/papers/performance-analysis/2411.12444v2.pdf

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:fc43df097912e6819fa88c3cc1ec7f04422ade24bbf69c8526006e67392aa076
+size 569351