// matrix_pitch.cu
#include <cuda_runtime.h>
#include <iostream>

#define CHECK_CUDA(call) \
    if ((call) != cudaSuccess) { \
        std::cerr << "CUDA error at " << __FILE__ << ":" << __LINE__ << " code=" << call << std::endl; \
        exit(1); \
    }

__global__ void matrixAddKernel(float* A, float* B, float* C, size_t pitch, int width, int height) {
    int x = blockIdx.x * blockDim.x + threadIdx.x;
    int y = blockIdx.y * blockDim.y + threadIdx.y;

    if (x < width && y < height) {
        // Convert pitched memory addresses
        float* rowA = (float*)((char*)A + y * pitch);
        float* rowB = (float*)((char*)B + y * pitch);
        float* rowC = (float*)((char*)C + y * pitch);
        rowC[x] = rowA[x] + rowB[x];
    }
}

int main() {
    const int width = 8;
    const int height = 6;
    const size_t elemSize = sizeof(float);

    float *h_A = new float[width * height];
    float *h_B = new float[width * height];
    float *h_C = new float[width * height];

    for (int i = 0; i < width * height; ++i) {
        h_A[i] = static_cast<float>(i);
        h_B[i] = static_cast<float>(i * 2);
    }

    float *d_A, *d_B, *d_C;
    size_t pitch;

    // Allocate pitched memory
    CHECK_CUDA(cudaMallocPitch(&d_A, &pitch, width * elemSize, height));
    CHECK_CUDA(cudaMallocPitch(&d_B, &pitch, width * elemSize, height));
    CHECK_CUDA(cudaMallocPitch(&d_C, &pitch, width * elemSize, height));

    // Copy host memory to device memory
    CHECK_CUDA(cudaMemcpy2D(d_A, pitch, h_A, width * elemSize, width * elemSize, height, cudaMemcpyHostToDevice));
    CHECK_CUDA(cudaMemcpy2D(d_B, pitch, h_B, width * elemSize, width * elemSize, height, cudaMemcpyHostToDevice));

    dim3 blockDim(16, 16);
    dim3 gridDim((width + blockDim.x - 1) / blockDim.x,
                 (height + blockDim.y - 1) / blockDim.y);

    matrixAddKernel<<<gridDim, blockDim>>>(d_A, d_B, d_C, pitch, width, height);
    CHECK_CUDA(cudaDeviceSynchronize());

    // Copy result back to host
    CHECK_CUDA(cudaMemcpy2D(h_C, width * elemSize, d_C, pitch, width * elemSize, height, cudaMemcpyDeviceToHost));

    // Print the result
    std::cout << "Result matrix C:\n";
    for (int y = 0; y < height; ++y) {
        for (int x = 0; x < width; ++x) {
            std::cout << h_C[y * width + x] << " ";
        }
        std::cout << "\n";
    }

    // Clean up
    delete[] h_A;
    delete[] h_B;
    delete[] h_C;
    cudaFree(d_A);
    cudaFree(d_B);
    cudaFree(d_C);

    return 0;
}

	.file	"tmpxft_00047f68_00000000-6_35.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3377:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3377:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.align 2
	.type	_ZNSolsEPFRSoS_E.isra.0, @function
_ZNSolsEPFRSoS_E.isra.0:
.LFB4012:
	.cfi_startproc
	jmp	*%rsi
	.cfi_endproc
.LFE4012:
	.size	_ZNSolsEPFRSoS_E.isra.0, .-_ZNSolsEPFRSoS_E.isra.0
	.globl	_Z42__device_stub__Z15matrixAddKernelPfS_S_miiPfS_S_mii
	.type	_Z42__device_stub__Z15matrixAddKernelPfS_S_miiPfS_S_mii, @function
_Z42__device_stub__Z15matrixAddKernelPfS_S_miiPfS_S_mii:
.LFB3399:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movl	%r9d, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L3
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z15matrixAddKernelPfS_S_mii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L3:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L5
	call	__stack_chk_fail@PLT
.L5:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3399:
	.size	_Z42__device_stub__Z15matrixAddKernelPfS_S_miiPfS_S_mii, .-_Z42__device_stub__Z15matrixAddKernelPfS_S_miiPfS_S_mii
	.globl	_Z15matrixAddKernelPfS_S_mii
	.type	_Z15matrixAddKernelPfS_S_mii, @function
_Z15matrixAddKernelPfS_S_mii:
.LFB3400:
	.cfi_startproc
	endbr64
	jmp	_Z42__device_stub__Z15matrixAddKernelPfS_S_miiPfS_S_mii
	.cfi_endproc
.LFE3400:
	.size	_Z15matrixAddKernelPfS_S_mii, .-_Z15matrixAddKernelPfS_S_mii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"CUDA error at "
.LC1:
	.string	"35.cu"
.LC2:
	.string	":"
.LC3:
	.string	" code="
.LC4:
	.string	"Result matrix C:\n"
.LC5:
	.string	" "
.LC6:
	.string	"\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3374:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$192, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	call	_Znam@PLT
	movl	$192, %edi
	movq	%rax, %r13
	call	_Znam@PLT
	movl	$192, %edi
	movq	%rax, %r12
	call	_Znam@PLT
	movq	%rax, %rbp
	xorl	%eax, %eax
.L10:
	cvtsi2ssl	%eax, %xmm0
	leal	(%rax,%rax), %edx
	movss	%xmm0, 0(%r13,%rax,4)
	cvtsi2ssl	%edx, %xmm0
	movss	%xmm0, (%r12,%rax,4)
	incq	%rax
	cmpq	$48, %rax
	jne	.L10
	leaq	40(%rsp), %r14
	leaq	16(%rsp), %r15
	movl	$6, %ecx
	movl	$32, %edx
	movq	%r14, %rsi
	movq	%r15, %rdi
	call	cudaMallocPitch@PLT
	testl	%eax, %eax
	je	.L11
	leaq	.LC0(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC1(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC2(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$42, %esi
	movq	%rax, %rdi
	jmp	.L26
.L11:
	leaq	24(%rsp), %r15
	movl	$6, %ecx
	movl	$32, %edx
	movq	%r14, %rsi
	movq	%r15, %rdi
	call	cudaMallocPitch@PLT
	testl	%eax, %eax
	je	.L12
	leaq	.LC0(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC1(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC2(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$43, %esi
	movq	%rax, %rdi
.L26:
	call	_ZNSolsEi@PLT
	leaq	.LC3(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$6, %ecx
	movq	%r14, %rsi
	movq	%r15, %rdi
	movl	$32, %edx
	movq	%rax, %rbp
	call	cudaMallocPitch@PLT
.L28:
	movl	%eax, %esi
.L29:
	movq	%rbp, %rdi
.L27:
	call	_ZNSolsEi@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movl	$1, %edi
	call	exit@PLT
.L12:
	leaq	32(%rsp), %r15
	movl	$6, %ecx
	movl	$32, %edx
	movq	%r14, %rsi
	movq	%r15, %rdi
	call	cudaMallocPitch@PLT
	testl	%eax, %eax
	je	.L13
	leaq	.LC0(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC1(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC2(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$44, %esi
	movq	%rax, %rdi
	jmp	.L26
.L13:
	pushq	%rax
	.cfi_remember_state
	.cfi_def_cfa_offset 152
	movl	$32, %ecx
	movq	%r13, %rdx
	movl	$6, %r9d
	pushq	$1
	.cfi_def_cfa_offset 160
	movq	56(%rsp), %rsi
	movl	$32, %r8d
	movq	32(%rsp), %rdi
	call	cudaMemcpy2D@PLT
	popq	%rdx
	.cfi_def_cfa_offset 152
	popq	%rcx
	.cfi_def_cfa_offset 144
	testl	%eax, %eax
	je	.L14
	leaq	.LC0(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC1(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC2(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$47, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC3(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$6, %r9d
	movl	$32, %ecx
	movq	%r13, %rdx
	movq	%rax, %rbp
	movl	$32, %r8d
	pushq	%rax
	.cfi_def_cfa_offset 152
	pushq	$1
	.cfi_def_cfa_offset 160
	movq	56(%rsp), %rsi
	movq	32(%rsp), %rdi
	jmp	.L30
.L14:
	.cfi_restore_state
	pushq	%rbx
	.cfi_def_cfa_offset 152
	movl	$6, %r9d
	movl	$32, %r8d
	movq	%r12, %rdx
	pushq	$1
	.cfi_def_cfa_offset 160
	movq	56(%rsp), %rsi
	movl	$32, %ecx
	movq	40(%rsp), %rdi
	call	cudaMemcpy2D@PLT
	popq	%r14
	.cfi_def_cfa_offset 152
	popq	%r15
	.cfi_def_cfa_offset 144
	testl	%eax, %eax
	je	.L15
	leaq	.LC0(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC1(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC2(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$48, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC3(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$6, %r9d
	movl	$32, %ecx
	movq	%r12, %rdx
	pushq	%r11
	.cfi_def_cfa_offset 152
	movq	%rax, %rbp
	movl	$32, %r8d
	pushq	$1
	.cfi_def_cfa_offset 160
	movq	56(%rsp), %rsi
	movq	40(%rsp), %rdi
.L30:
	call	cudaMemcpy2D@PLT
	popq	%r9
	.cfi_def_cfa_offset 152
	popq	%r10
	.cfi_def_cfa_offset 144
	movl	%eax, %esi
	jmp	.L29
.L15:
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movl	$1, %esi
	movabsq	$68719476752, %rdx
	movabsq	$4294967297, %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L16
	movq	40(%rsp), %rcx
	movq	32(%rsp), %rdx
	movl	$6, %r9d
	movl	$8, %r8d
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdi
	call	_Z42__device_stub__Z15matrixAddKernelPfS_S_miiPfS_S_mii
.L16:
	call	cudaDeviceSynchronize@PLT
	testl	%eax, %eax
	je	.L17
	leaq	.LC0(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC1(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC2(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$55, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC3(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rbp
	call	cudaDeviceSynchronize@PLT
	jmp	.L28
.L17:
	pushq	%rsi
	.cfi_def_cfa_offset 152
	movl	$32, %r8d
	movq	%rbp, %rdi
	movl	$6, %r9d
	pushq	$2
	.cfi_def_cfa_offset 160
	movq	56(%rsp), %rcx
	movl	$32, %esi
	movq	48(%rsp), %rdx
	call	cudaMemcpy2D@PLT
	popq	%rdi
	.cfi_def_cfa_offset 152
	popq	%r8
	.cfi_def_cfa_offset 144
	testl	%eax, %eax
	je	.L18
	leaq	.LC0(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC1(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC2(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$58, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC3(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$32, %esi
	movq	%rbp, %rdi
	movl	$6, %r9d
	movq	%rax, %r12
	pushq	%rax
	.cfi_def_cfa_offset 152
	movl	$32, %r8d
	pushq	$2
	.cfi_def_cfa_offset 160
	movq	56(%rsp), %rcx
	movq	48(%rsp), %rdx
	call	cudaMemcpy2D@PLT
	popq	%rdx
	.cfi_def_cfa_offset 152
	movq	%r12, %rdi
	popq	%rcx
	.cfi_def_cfa_offset 144
	movl	%eax, %esi
	jmp	.L27
.L18:
	leaq	_ZSt4cout(%rip), %r14
	leaq	.LC4(%rip), %rsi
	xorl	%ebx, %ebx
	movq	%r14, %rdi
	leaq	.LC5(%rip), %r15
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
.L19:
	movq	%rbx, %rax
	xorl	%edx, %edx
	salq	$5, %rax
	addq	%rbp, %rax
	movq	%rax, (%rsp)
.L20:
	movq	(%rsp), %rax
	movq	%r14, %rdi
	movq	%rdx, 8(%rsp)
	cvtss2sd	(%rax,%rdx,4), %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	%r15, %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	8(%rsp), %rdx
	incq	%rdx
	cmpq	$8, %rdx
	jne	.L20
	leaq	.LC6(%rip), %rsi
	movq	%r14, %rdi
	incq	%rbx
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	cmpq	$6, %rbx
	jne	.L19
	movq	%r13, %rdi
	call	_ZdaPv@PLT
	movq	%r12, %rdi
	call	_ZdaPv@PLT
	movq	%rbp, %rdi
	call	_ZdaPv@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L22
	call	__stack_chk_fail@PLT
.L22:
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3374:
	.size	main, .-main
	.section	.rodata.str1.1
.LC7:
	.string	"_Z15matrixAddKernelPfS_S_mii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3402:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC7(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z15matrixAddKernelPfS_S_mii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3402:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.text.startup
	.type	_GLOBAL__sub_I_main, @function
_GLOBAL__sub_I_main:
.LFB4009:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	leaq	_ZStL8__ioinit(%rip), %rbp
	movq	%rbp, %rdi
	call	_ZNSt8ios_base4InitC1Ev@PLT
	movq	_ZNSt8ios_base4InitD1Ev@GOTPCREL(%rip), %rdi
	movq	%rbp, %rsi
	popq	%rbp
	.cfi_def_cfa_offset 8
	leaq	__dso_handle(%rip), %rdx
	jmp	__cxa_atexit@PLT
	.cfi_endproc
.LFE4009:
	.size	_GLOBAL__sub_I_main, .-_GLOBAL__sub_I_main
	.section	.init_array
	.align 8
	.quad	_GLOBAL__sub_I_main
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZStL8__ioinit
	.comm	_ZStL8__ioinit,1,1
	.hidden	__dso_handle
	.ident	"GCC: (Ubuntu 11.4.0-1ubuntu1~22.04) 11.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

// matrix_pitch_amd.cpp
#include <hip/hip_runtime.h>
#include <iostream>

#define CHECK_HIP(call) \
    if ((call) != hipSuccess) { \
        std::cerr << "HIP error at " << __FILE__ << ":" << __LINE__ << " code=" << call << std::endl; \
        exit(1); \
    }

__global__ void matrixAddKernel(float* A, float* B, float* C, size_t pitch, int width, int height) {
    int x = hipBlockIdx_x * hipBlockDim_x + hipThreadIdx_x;
    int y = hipBlockIdx_y * hipBlockDim_y + hipThreadIdx_y;

    if (x < width && y < height) {
        float* rowA = (float*)((char*)A + y * pitch);
        float* rowB = (float*)((char*)B + y * pitch);
        float* rowC = (float*)((char*)C + y * pitch);
        rowC[x] = rowA[x] + rowB[x];
    }
}

int main() {
    const int width = 8;
    const int height = 6;
    const size_t elemSize = sizeof(float);

    float *h_A = new float[width * height];
    float *h_B = new float[width * height];
    float *h_C = new float[width * height];

    for (int i = 0; i < width * height; ++i) {
        h_A[i] = static_cast<float>(i);
        h_B[i] = static_cast<float>(i * 2);
    }

    float *d_A, *d_B, *d_C;
    size_t pitch;

    // Allocate pitched memory
    CHECK_HIP(hipMallocPitch((void**)&d_A, &pitch, width * elemSize, height));
    CHECK_HIP(hipMallocPitch((void**)&d_B, &pitch, width * elemSize, height));
    CHECK_HIP(hipMallocPitch((void**)&d_C, &pitch, width * elemSize, height));

    // Copy host memory to device memory
    CHECK_HIP(hipMemcpy2D(d_A, pitch, h_A, width * elemSize, width * elemSize, height, hipMemcpyHostToDevice));
    CHECK_HIP(hipMemcpy2D(d_B, pitch, h_B, width * elemSize, width * elemSize, height, hipMemcpyHostToDevice));

    dim3 blockDim(16, 16);
    dim3 gridDim((width + blockDim.x - 1) / blockDim.x,
                 (height + blockDim.y - 1) / blockDim.y);

    hipLaunchKernelGGL(matrixAddKernel, gridDim, blockDim, 0, 0, d_A, d_B, d_C, pitch, width, height);
    CHECK_HIP(hipDeviceSynchronize());

    // Copy result back to host
    CHECK_HIP(hipMemcpy2D(h_C, width * elemSize, d_C, pitch, width * elemSize, height, hipMemcpyDeviceToHost));

    // Print the result
    std::cout << "Result matrix C:\n";
    for (int y = 0; y < height; ++y) {
        for (int x = 0; x < width; ++x) {
            std::cout << h_C[y * width + x] << " ";
        }
        std::cout << "\n";
    }

    // Clean up
    delete[] h_A;
    delete[] h_B;
    delete[] h_C;
    hipFree(d_A);
    hipFree(d_B);
    hipFree(d_C);

    return 0;
}

	.text
	.file	"35.cpp"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z30__device_stub__matrixAddKernelPfS_S_mii # -- Begin function _Z30__device_stub__matrixAddKernelPfS_S_mii
	.p2align	4, 0x90
	.type	_Z30__device_stub__matrixAddKernelPfS_S_mii,@function
_Z30__device_stub__matrixAddKernelPfS_S_mii: # @_Z30__device_stub__matrixAddKernelPfS_S_mii
	.cfi_startproc
# %bb.0:
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 88(%rsp)
	movq	%rsi, 80(%rsp)
	movq	%rdx, 72(%rsp)
	movq	%rcx, 64(%rsp)
	movl	%r8d, 12(%rsp)
	movl	%r9d, 8(%rsp)
	leaq	88(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	48(%rsp), %rdi
	leaq	32(%rsp), %rsi
	leaq	24(%rsp), %rdx
	leaq	16(%rsp), %rcx
	callq	__hipPopCallConfiguration
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	movq	32(%rsp), %rcx
	movl	40(%rsp), %r8d
	leaq	96(%rsp), %r9
	movl	$_Z15matrixAddKernelPfS_S_mii, %edi
	pushq	16(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	32(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$168, %rsp
	.cfi_adjust_cfa_offset -168
	retq
.Lfunc_end0:
	.size	_Z30__device_stub__matrixAddKernelPfS_S_mii, .Lfunc_end0-_Z30__device_stub__matrixAddKernelPfS_S_mii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.p2align	4, 0x90
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$200, %rsp
	.cfi_def_cfa_offset 256
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$192, %edi
	callq	_Znam
	movq	%rax, %rbx
	movl	$192, %edi
	callq	_Znam
	movq	%rax, %r14
	movl	$192, %edi
	callq	_Znam
	movq	%rax, %r15
	xorl	%eax, %eax
	xorl	%ecx, %ecx
	.p2align	4, 0x90
.LBB1_1:                                # =>This Inner Loop Header: Depth=1
	xorps	%xmm0, %xmm0
	cvtsi2ss	%ecx, %xmm0
	movss	%xmm0, (%rbx,%rcx,4)
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	movss	%xmm0, (%r14,%rcx,4)
	incq	%rcx
	addl	$2, %eax
	cmpq	$48, %rcx
	jne	.LBB1_1
# %bb.2:
	leaq	48(%rsp), %rdi
	leaq	24(%rsp), %rsi
	movl	$32, %edx
	movl	$6, %ecx
	callq	hipMallocPitch
	testl	%eax, %eax
	jne	.LBB1_3
# %bb.5:
	leaq	40(%rsp), %rdi
	leaq	24(%rsp), %rsi
	movl	$32, %edx
	movl	$6, %ecx
	callq	hipMallocPitch
	testl	%eax, %eax
	jne	.LBB1_6
# %bb.7:
	leaq	32(%rsp), %rdi
	leaq	24(%rsp), %rsi
	movl	$32, %edx
	movl	$6, %ecx
	callq	hipMallocPitch
	testl	%eax, %eax
	jne	.LBB1_8
# %bb.9:
	movq	48(%rsp), %rdi
	movq	24(%rsp), %rsi
	movl	$1, (%rsp)
	movl	$32, %ecx
	movl	$32, %r8d
	movl	$6, %r9d
	movq	%rbx, %rdx
	callq	hipMemcpy2D
	testl	%eax, %eax
	jne	.LBB1_10
# %bb.11:
	movq	40(%rsp), %rdi
	movq	24(%rsp), %rsi
	movl	$1, (%rsp)
	movl	$32, %ecx
	movl	$32, %r8d
	movl	$6, %r9d
	movq	%r14, %rdx
	callq	hipMemcpy2D
	testl	%eax, %eax
	jne	.LBB1_12
# %bb.16:
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	movabsq	$68719476752, %rdx              # imm = 0x1000000010
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_18
# %bb.17:
	movq	48(%rsp), %rax
	movq	40(%rsp), %rcx
	movq	32(%rsp), %rdx
	movq	24(%rsp), %rsi
	movq	%rax, 136(%rsp)
	movq	%rcx, 128(%rsp)
	movq	%rdx, 120(%rsp)
	movq	%rsi, 112(%rsp)
	movl	$8, 60(%rsp)
	movl	$6, 56(%rsp)
	leaq	136(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	128(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	120(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	112(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	60(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	96(%rsp), %rdi
	leaq	80(%rsp), %rsi
	leaq	72(%rsp), %rdx
	leaq	64(%rsp), %rcx
	callq	__hipPopCallConfiguration
	movq	72(%rsp), %rax
	movq	64(%rsp), %rdi
	movq	96(%rsp), %rsi
	movl	104(%rsp), %edx
	movq	80(%rsp), %rcx
	movl	88(%rsp), %r8d
	movq	%rdi, 8(%rsp)
	movq	%rax, (%rsp)
	leaq	144(%rsp), %r9
	movl	$_Z15matrixAddKernelPfS_S_mii, %edi
	callq	hipLaunchKernel
.LBB1_18:
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB1_19
# %bb.20:
	movq	32(%rsp), %rdx
	movq	24(%rsp), %rcx
	movl	$2, (%rsp)
	movl	$32, %esi
	movl	$32, %r8d
	movl	$6, %r9d
	movq	%r15, %rdi
	callq	hipMemcpy2D
	testl	%eax, %eax
	jne	.LBB1_21
# %bb.22:
	movl	$_ZSt4cout, %edi
	movl	$.L.str.4, %esi
	movl	$17, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	xorl	%r12d, %r12d
	movq	%r15, %r13
	.p2align	4, 0x90
.LBB1_23:                               # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_24 Depth 2
	xorl	%ebp, %ebp
	.p2align	4, 0x90
.LBB1_24:                               #   Parent Loop BB1_23 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movss	(%r13,%rbp,4), %xmm0            # xmm0 = mem[0],zero,zero,zero
	cvtss2sd	%xmm0, %xmm0
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movl	$.L.str.5, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	incq	%rbp
	cmpq	$8, %rbp
	jne	.LBB1_24
# %bb.25:                               #   in Loop: Header=BB1_23 Depth=1
	movl	$_ZSt4cout, %edi
	movl	$.L.str.6, %esi
	movl	$1, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	incq	%r12
	addq	$32, %r13
	cmpq	$6, %r12
	jne	.LBB1_23
# %bb.26:
	movq	%rbx, %rdi
	callq	_ZdaPv
	movq	%r14, %rdi
	callq	_ZdaPv
	movq	%r15, %rdi
	callq	_ZdaPv
	movq	48(%rsp), %rdi
	callq	hipFree
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$200, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB1_3:
	.cfi_def_cfa_offset 256
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.1, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.2, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	movl	$41, %esi
	callq	_ZNSolsEi
	movl	$.L.str.3, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rbx
	leaq	48(%rsp), %rdi
	jmp	.LBB1_4
.LBB1_6:
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.1, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.2, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	movl	$42, %esi
	callq	_ZNSolsEi
	movl	$.L.str.3, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rbx
	leaq	40(%rsp), %rdi
	jmp	.LBB1_4
.LBB1_8:
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.1, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.2, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	movl	$43, %esi
	callq	_ZNSolsEi
	movl	$.L.str.3, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rbx
	leaq	32(%rsp), %rdi
.LBB1_4:
	leaq	24(%rsp), %rsi
	movl	$32, %edx
	movl	$6, %ecx
	callq	hipMallocPitch
	jmp	.LBB1_14
.LBB1_10:
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.1, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.2, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	movl	$46, %esi
	callq	_ZNSolsEi
	movl	$.L.str.3, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %r14
	movq	48(%rsp), %rdi
	movq	24(%rsp), %rsi
	movl	$1, (%rsp)
	movl	$32, %ecx
	movl	$32, %r8d
	movl	$6, %r9d
	movq	%rbx, %rdx
	callq	hipMemcpy2D
	movq	%r14, %rdi
	jmp	.LBB1_15
.LBB1_12:
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.1, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.2, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	movl	$47, %esi
	callq	_ZNSolsEi
	movl	$.L.str.3, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rbx
	movq	40(%rsp), %rdi
	movq	24(%rsp), %rsi
	movl	$1, (%rsp)
	movl	$32, %ecx
	movl	$32, %r8d
	movl	$6, %r9d
	movq	%r14, %rdx
	jmp	.LBB1_13
.LBB1_19:
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.1, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.2, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	movl	$54, %esi
	callq	_ZNSolsEi
	movl	$.L.str.3, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rbx
	callq	hipDeviceSynchronize
	jmp	.LBB1_14
.LBB1_21:
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.1, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.2, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	movl	$57, %esi
	callq	_ZNSolsEi
	movl	$.L.str.3, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rbx
	movq	32(%rsp), %rdx
	movq	24(%rsp), %rcx
	movl	$2, (%rsp)
	movl	$32, %esi
	movl	$32, %r8d
	movl	$6, %r9d
	movq	%r15, %rdi
.LBB1_13:
	callq	hipMemcpy2D
.LBB1_14:
	movq	%rbx, %rdi
.LBB1_15:
	movl	%eax, %esi
	callq	_ZNSolsEi
	movq	%rax, %rdi
	callq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
	movl	$1, %edi
	callq	exit
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	cmpq	$0, __hip_gpubin_handle(%rip)
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	movq	__hip_gpubin_handle(%rip), %rdi
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15matrixAddKernelPfS_S_mii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z15matrixAddKernelPfS_S_mii,@object # @_Z15matrixAddKernelPfS_S_mii
	.section	.rodata,"a",@progbits
	.globl	_Z15matrixAddKernelPfS_S_mii
	.p2align	3, 0x0
_Z15matrixAddKernelPfS_S_mii:
	.quad	_Z30__device_stub__matrixAddKernelPfS_S_mii
	.size	_Z15matrixAddKernelPfS_S_mii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"HIP error at "
	.size	.L.str, 14

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"35.cpp"
	.size	.L.str.1, 7

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	":"
	.size	.L.str.2, 2

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	" code="
	.size	.L.str.3, 7

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"Result matrix C:\n"
	.size	.L.str.4, 18

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	" "
	.size	.L.str.5, 2

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"\n"
	.size	.L.str.6, 2

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z15matrixAddKernelPfS_S_mii"
	.size	.L__unnamed_1, 29

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.section	".linker-options","e",@llvm_linker_options
	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z30__device_stub__matrixAddKernelPfS_S_mii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z15matrixAddKernelPfS_S_mii
	.addrsig_sym _ZSt4cerr
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z15matrixAddKernelPfS_S_mii ; -- Begin function _Z15matrixAddKernelPfS_S_mii
	.globl	_Z15matrixAddKernelPfS_S_mii
	.p2align	8
	.type	_Z15matrixAddKernelPfS_S_mii,@function
_Z15matrixAddKernelPfS_S_mii:           ; @_Z15matrixAddKernelPfS_S_mii
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x34
	s_load_b64 s[2:3], s[0:1], 0x20
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s4, 0xffff
	s_lshr_b32 s4, s4, 16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
	v_cmp_gt_i32_e32 vcc_lo, s2, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s2, s3, v1
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_load_b256 s[0:7], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_waitcnt lgkmcnt(0)
	v_mul_lo_u32 v4, v1, s7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v5, v2, s6
	v_mad_u64_u32 v[2:3], null, v1, s6, 0
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add3_u32 v7, v3, v4, v5
	v_add_co_u32 v3, vcc_lo, s0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v7, vcc_lo
	v_add_co_u32 v5, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v6, vcc_lo, s3, v7, vcc_lo
	v_add_co_u32 v3, vcc_lo, v3, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v4, vcc_lo, v4, v1, vcc_lo
	v_add_co_u32 v5, vcc_lo, v5, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, v6, v1, vcc_lo
	global_load_b32 v3, v[3:4], off
	global_load_b32 v4, v[5:6], off
	v_add_co_u32 v2, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v7, vcc_lo
	v_add_co_u32 v0, vcc_lo, v2, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v5, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v3, v3, v4
	global_store_b32 v[0:1], v3, off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15matrixAddKernelPfS_S_mii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z15matrixAddKernelPfS_S_mii, .Lfunc_end0-_Z15matrixAddKernelPfS_S_mii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 304
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z15matrixAddKernelPfS_S_mii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z15matrixAddKernelPfS_S_mii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
