#include <cuda_runtime.h>
#include <cuda.h>
#include <stdio.h>
#include <math.h>

// CUDA kernel for batch normalization forward pass
__global__ void batchNormForwardKernel(
    float* input,             // Input data [N,C,H,W]
    float* output,            // Output data [N,C,H,W]
    float* gamma,             // Scale parameter [C]
    float* beta,              // Shift parameter [C]
    float* running_mean,      // Running mean [C]
    float* running_var,       // Running variance [C]
    float* batch_mean,        // Batch mean [C]
    float* batch_var,         // Batch variance [C]
    int N, int C, int H, int W,
    float epsilon,            // Small constant for numerical stability
    float momentum,           // Momentum for running averages
    bool training             // Whether in training mode
) {
    // Get channel index
    const int c = blockIdx.x;
    
    if (c >= C) return;
    
    // Each thread block handles one channel
    const int thread_id = threadIdx.x;
    const int block_size = blockDim.x;
    
    const int spatial_size = H * W;
    const int feature_map_size = N * spatial_size;
    
    // Pointer to the start of this channel's data
    const float* channel_input = input + c * spatial_size;
    float* channel_output = output + c * spatial_size;
    
    // Compute mean and variance for this channel (training mode only)
    if (training) {
        float sum = 0.0f;
        float sq_sum = 0.0f;
        
        // Parallel reduction for mean computation
        for (int i = thread_id; i < feature_map_size; i += block_size) {
            int n = i / spatial_size;
            int hw = i % spatial_size;
            float val = channel_input[n * C * spatial_size + hw];
            sum += val;
            sq_sum += val * val;
        }
        
        // Warp-level reduction
        for (int stride = block_size / 2; stride > 0; stride >>= 1) {
            sum += __shfl_down_sync(0xffffffff, sum, stride);
            sq_sum += __shfl_down_sync(0xffffffff, sq_sum, stride);
        }
        
        // First thread in the block writes the result
        if (thread_id == 0) {
            float mean = sum / feature_map_size;
            float variance = (sq_sum / feature_map_size) - (mean * mean);
            
            batch_mean[c] = mean;
            batch_var[c] = variance;
            
            // Update running stats
            running_mean[c] = momentum * running_mean[c] + (1.0f - momentum) * mean;
            running_var[c] = momentum * running_var[c] + (1.0f - momentum) * variance;
        }
    }
    
    // Make sure batch stats are available to all threads
    __syncthreads();
    
    // Apply normalization
    for (int i = thread_id; i < feature_map_size; i += block_size) {
        int n = i / spatial_size;
        int hw = i % spatial_size;
        int idx = n * C * spatial_size + c * spatial_size + hw;
        
        float mean_val = training ? batch_mean[c] : running_mean[c];
        float var_val = training ? batch_var[c] : running_var[c];
        
        float normalized = (input[idx] - mean_val) / sqrtf(var_val + epsilon);
        output[idx] = gamma[c] * normalized + beta[c];
    }
}

// Host function to launch the batch normalization kernel
void batchNormForward(
    float* d_input,
    float* d_output,
    float* d_gamma,
    float* d_beta,
    float* d_running_mean,
    float* d_running_var,
    float* d_batch_mean,
    float* d_batch_var,
    int N, int C, int H, int W,
    float epsilon,
    float momentum,
    bool training,
    cudaStream_t stream = 0
) {
    // Configure kernel launch parameters
    dim3 blocks(C);
    int threadsPerBlock = 256;  // Can be tuned for better performance
    
    batchNormForwardKernel<<<blocks, threadsPerBlock, 0, stream>>>(
        d_input, d_output, d_gamma, d_beta,
        d_running_mean, d_running_var,
        d_batch_mean, d_batch_var,
        N, C, H, W, epsilon, momentum, training
    );
}

// Additional backward pass kernel for training
__global__ void batchNormBackwardKernel(
    float* input,             // Input data [N,C,H,W]
    float* d_output,          // Gradient w.r.t output [N,C,H,W]
    float* d_input,           // Gradient w.r.t input [N,C,H,W]
    float* gamma,             // Scale parameter [C]
    float* d_gamma,           // Gradient w.r.t gamma [C]
    float* d_beta,            // Gradient w.r.t beta [C]
    float* batch_mean,        // Batch mean [C]
    float* batch_var,         // Batch variance [C]
    int N, int C, int H, int W,
    float epsilon             // Small constant for numerical stability
) {
    // Get channel index
    const int c = blockIdx.x;
    
    if (c >= C) return;
    
    // Each thread block handles one channel
    const int thread_id = threadIdx.x;
    const int block_size = blockDim.x;
    
    const int spatial_size = H * W;
    const int feature_map_size = N * spatial_size;
    
    // Calculate intermediate sums for backprop
    float sum_dy = 0.0f;
    float sum_dy_x = 0.0f;
    
    for (int i = thread_id; i < feature_map_size; i += block_size) {
        int n = i / spatial_size;
        int hw = i % spatial_size;
        int idx = n * C * spatial_size + c * spatial_size + hw;
        
        float dy = d_output[idx];
        float x = (input[idx] - batch_mean[c]) / sqrtf(batch_var[c] + epsilon);
        
        sum_dy += dy;
        sum_dy_x += dy * x;
    }
    
    // Warp-level reduction
    for (int stride = block_size / 2; stride > 0; stride >>= 1) {
        sum_dy += __shfl_down_sync(0xffffffff, sum_dy, stride);
        sum_dy_x += __shfl_down_sync(0xffffffff, sum_dy_x, stride);
    }
    
    // First thread in the block updates gradients for gamma and beta
    if (thread_id == 0) {
        d_beta[c] = sum_dy;
        d_gamma[c] = sum_dy_x;
    }
    
    __syncthreads();
    
    // Calculate gradients with respect to input
    float inv_std = 1.0f / sqrtf(batch_var[c] + epsilon);
    float N_inv = 1.0f / feature_map_size;
    
    for (int i = thread_id; i < feature_map_size; i += block_size) {
        int n = i / spatial_size;
        int hw = i % spatial_size;
        int idx = n * C * spatial_size + c * spatial_size + hw;
        
        float dy = d_output[idx];
        float x = input[idx] - batch_mean[c];
        
        // Apply chain rule for the backward pass
        d_input[idx] = gamma[c] * inv_std * (dy - (sum_dy + x * inv_std * sum_dy_x) * N_inv);
    }
}

// Host function to launch the batch normalization backward kernel
void batchNormBackward(
    float* d_input,
    float* d_output,
    float* d_d_input,
    float* d_gamma,
    float* d_d_gamma,
    float* d_d_beta,
    float* d_batch_mean,
    float* d_batch_var,
    int N, int C, int H, int W,
    float epsilon,
    cudaStream_t stream = 0
) {
    // Configure kernel launch parameters
    dim3 blocks(C);
    int threadsPerBlock = 256;  // Can be tuned for better performance
    
    batchNormBackwardKernel<<<blocks, threadsPerBlock, 0, stream>>>(
        d_input, d_output, d_d_input, d_gamma, d_d_gamma, d_d_beta,
        d_batch_mean, d_batch_var,
        N, C, H, W, epsilon
    );
}

// Simple test function to demonstrate usage
void testBatchNorm() {
    // Example dimensions
    const int N = 32;    // Batch size
    const int C = 64;    // Channels
    const int H = 28;    // Height
    const int W = 28;    // Width
    
    const int input_size = N * C * H * W;
    const int params_size = C;
    
    // Allocate host memory
    float* h_input = new float[input_size];
    float* h_output = new float[input_size];
    float* h_gamma = new float[params_size];
    float* h_beta = new float[params_size];
    float* h_running_mean = new float[params_size];
    float* h_running_var = new float[params_size];
    float* h_batch_mean = new float[params_size];
    float* h_batch_var = new float[params_size];
    
    // Initialize data (would normally come from your network)
    for (int i = 0; i < input_size; ++i) {
        h_input[i] = static_cast<float>(rand()) / RAND_MAX;
    }
    for (int i = 0; i < params_size; ++i) {
        h_gamma[i] = 1.0f;  // Initialize to 1
        h_beta[i] = 0.0f;   // Initialize to 0
        h_running_mean[i] = 0.0f;
        h_running_var[i] = 1.0f;
    }
    
    // Allocate device memory
    float *d_input, *d_output;
    float *d_gamma, *d_beta;
    float *d_running_mean, *d_running_var;
    float *d_batch_mean, *d_batch_var;
    
    cudaMalloc(&d_input, input_size * sizeof(float));
    cudaMalloc(&d_output, input_size * sizeof(float));
    cudaMalloc(&d_gamma, params_size * sizeof(float));
    cudaMalloc(&d_beta, params_size * sizeof(float));
    cudaMalloc(&d_running_mean, params_size * sizeof(float));
    cudaMalloc(&d_running_var, params_size * sizeof(float));
    cudaMalloc(&d_batch_mean, params_size * sizeof(float));
    cudaMalloc(&d_batch_var, params_size * sizeof(float));
    
    // Copy data to device
    cudaMemcpy(d_input, h_input, input_size * sizeof(float), cudaMemcpyHostToDevice);
    cudaMemcpy(d_gamma, h_gamma, params_size * sizeof(float), cudaMemcpyHostToDevice);
    cudaMemcpy(d_beta, h_beta, params_size * sizeof(float), cudaMemcpyHostToDevice);
    cudaMemcpy(d_running_mean, h_running_mean, params_size * sizeof(float), cudaMemcpyHostToDevice);
    cudaMemcpy(d_running_var, h_running_var, params_size * sizeof(float), cudaMemcpyHostToDevice);
    
    // Run batch normalization
    const float epsilon = 1e-5f;
    const float momentum = 0.1f;
    const bool training = true;
    
    batchNormForward(
        d_input, d_output, d_gamma, d_beta,
        d_running_mean, d_running_var,
        d_batch_mean, d_batch_var,
        N, C, H, W, epsilon, momentum, training
    );
    
    // Copy results back to host
    cudaMemcpy(h_output, d_output, input_size * sizeof(float), cudaMemcpyDeviceToHost);
    cudaMemcpy(h_batch_mean, d_batch_mean, params_size * sizeof(float), cudaMemcpyDeviceToHost);
    cudaMemcpy(h_batch_var, d_batch_var, params_size * sizeof(float), cudaMemcpyDeviceToHost);
    
    // Print some results for verification
    printf("Batch normalization completed\n");
    printf("First few values of the output:\n");
    for (int i = 0; i < 5; ++i) {
        printf("%f ", h_output[i]);
    }
    printf("\n");
    
    // Clean up
    delete[] h_input;
    delete[] h_output;
    delete[] h_gamma;
    delete[] h_beta;
    delete[] h_running_mean;
    delete[] h_running_var;
    delete[] h_batch_mean;
    delete[] h_batch_var;
    
    cudaFree(d_input);
    cudaFree(d_output);
    cudaFree(d_gamma);
    cudaFree(d_beta);
    cudaFree(d_running_mean);
    cudaFree(d_running_var);
    cudaFree(d_batch_mean);
    cudaFree(d_batch_var);
}

int main() {
    // Initialize CUDA
    cudaFree(0);  // Simple way to initialize the CUDA runtime
    
    // Run the batch normalization test
    testBatchNorm();
    
    printf("Batch normalization test completed successfully!\n");
    return 0;
}
	.file	"tmpxft_00047d64_00000000-6_20.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB1985:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE1985:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.type	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0, @function
_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0:
.LFB2129:
	.cfi_startproc
	jmp	cudaMalloc@PLT
	.cfi_endproc
.LFE2129:
	.size	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0, .-_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	.globl	_Z63__device_stub__Z22batchNormForwardKernelPfS_S_S_S_S_S_S_iiiiffbPfS_S_S_S_S_S_S_iiiiffb
	.type	_Z63__device_stub__Z22batchNormForwardKernelPfS_S_S_S_S_S_S_iiiiffbPfS_S_S_S_S_S_S_iiiiffb, @function
_Z63__device_stub__Z22batchNormForwardKernelPfS_S_S_S_S_S_S_iiiiffbPfS_S_S_S_S_S_S_iiiiffb:
.LFB2007:
	.cfi_startproc
	endbr64
	subq	$280, %rsp
	.cfi_def_cfa_offset 288
	movq	288(%rsp), %rax
	movq	%rdi, 72(%rsp)
	leaq	96(%rsp), %rdi
	movq	%rsi, 64(%rsp)
	leaq	108(%rsp), %rsi
	movq	%rax, 24(%rsp)
	movq	296(%rsp), %rax
	movq	%rdx, 56(%rsp)
	leaq	80(%rsp), %rdx
	movq	%rax, 16(%rsp)
	movl	336(%rsp), %eax
	movq	%rcx, 48(%rsp)
	leaq	88(%rsp), %rcx
	movq	%r8, 40(%rsp)
	movq	%r9, 32(%rsp)
	movb	%al, 4(%rsp)
	movss	%xmm0, 12(%rsp)
	movss	%xmm1, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 264(%rsp)
	xorl	%eax, %eax
	leaq	72(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	304(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	312(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	320(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	328(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 256(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 96(%rsp)
	movl	$1, 104(%rsp)
	movq	%rax, 108(%rsp)
	movl	$1, 116(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L3
	pushq	88(%rsp)
	.cfi_def_cfa_offset 296
	leaq	_Z22batchNormForwardKernelPfS_S_S_S_S_S_S_iiiiffb(%rip), %rdi
	pushq	88(%rsp)
	.cfi_def_cfa_offset 304
	movq	124(%rsp), %rcx
	movl	132(%rsp), %r8d
	movq	112(%rsp), %rsi
	movl	120(%rsp), %edx
	leaq	160(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 296
	popq	%rdx
	.cfi_def_cfa_offset 288
.L3:
	movq	264(%rsp), %rax
	subq	%fs:40, %rax
	je	.L5
	call	__stack_chk_fail@PLT
.L5:
	addq	$280, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2007:
	.size	_Z63__device_stub__Z22batchNormForwardKernelPfS_S_S_S_S_S_S_iiiiffbPfS_S_S_S_S_S_S_iiiiffb, .-_Z63__device_stub__Z22batchNormForwardKernelPfS_S_S_S_S_S_S_iiiiffbPfS_S_S_S_S_S_S_iiiiffb
	.globl	_Z22batchNormForwardKernelPfS_S_S_S_S_S_S_iiiiffb
	.type	_Z22batchNormForwardKernelPfS_S_S_S_S_S_S_iiiiffb, @function
_Z22batchNormForwardKernelPfS_S_S_S_S_S_S_iiiiffb:
.LFB2008:
	.cfi_startproc
	endbr64
	movzbl	56(%rsp), %eax
	movl	%eax, 56(%rsp)
	jmp	_Z63__device_stub__Z22batchNormForwardKernelPfS_S_S_S_S_S_S_iiiiffbPfS_S_S_S_S_S_S_iiiiffb
	.cfi_endproc
.LFE2008:
	.size	_Z22batchNormForwardKernelPfS_S_S_S_S_S_S_iiiiffb, .-_Z22batchNormForwardKernelPfS_S_S_S_S_S_S_iiiiffb
	.globl	_Z16batchNormForwardPfS_S_S_S_S_S_S_iiiiffbP11CUstream_st
	.type	_Z16batchNormForwardPfS_S_S_S_S_S_S_iiiiffbP11CUstream_st, @function
_Z16batchNormForwardPfS_S_S_S_S_S_S_iiiiffbP11CUstream_st:
.LFB1979:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%r9, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%r8, %rbx
	xorl	%r8d, %r8d
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	movl	208(%rsp), %eax
	movl	184(%rsp), %r12d
	movq	%rdi, 8(%rsp)
	movl	192(%rsp), %r10d
	movl	200(%rsp), %r11d
	movq	%rsi, 16(%rsp)
	movl	%eax, 44(%rsp)
	movq	216(%rsp), %r9
	movabsq	$4294967297, %rax
	movq	%rax, 76(%rsp)
	movl	80(%rsp), %esi
	movq	%rdx, 24(%rsp)
	movl	$16777217, %edx
	movq	160(%rsp), %r13
	movl	%r12d, 72(%rsp)
	movq	72(%rsp), %rdi
	salq	$8, %rdx
	movq	%rcx, 32(%rsp)
	movl	$1, %ecx
	movq	168(%rsp), %r14
	movl	%r10d, 60(%rsp)
	movl	176(%rsp), %r15d
	movl	%r11d, 56(%rsp)
	movss	%xmm0, 52(%rsp)
	movss	%xmm1, 48(%rsp)
	call	__cudaPushCallConfiguration@PLT
	movss	48(%rsp), %xmm1
	movss	52(%rsp), %xmm0
	testl	%eax, %eax
	movl	56(%rsp), %r11d
	movl	60(%rsp), %r10d
	jne	.L9
	movzbl	44(%rsp), %eax
	movl	%r12d, 184(%rsp)
	movq	%rbp, %r9
	movq	%rbx, %r8
	movl	%r15d, 176(%rsp)
	movq	32(%rsp), %rcx
	movq	%r14, 168(%rsp)
	movq	24(%rsp), %rdx
	movq	%r13, 160(%rsp)
	movq	16(%rsp), %rsi
	movl	%eax, 208(%rsp)
	movq	8(%rsp), %rdi
	movl	%r11d, 200(%rsp)
	movl	%r10d, 192(%rsp)
	addq	$104, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z63__device_stub__Z22batchNormForwardKernelPfS_S_S_S_S_S_S_iiiiffbPfS_S_S_S_S_S_S_iiiiffb
.L9:
	.cfi_restore_state
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE1979:
	.size	_Z16batchNormForwardPfS_S_S_S_S_S_S_iiiiffbP11CUstream_st, .-_Z16batchNormForwardPfS_S_S_S_S_S_S_iiiiffbP11CUstream_st
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC4:
	.string	"Batch normalization completed\n"
.LC5:
	.string	"First few values of the output:\n"
.LC6:
	.string	"%f "
.LC7:
	.string	"\n"
	.text
	.globl	_Z13testBatchNormv
	.type	_Z13testBatchNormv, @function
_Z13testBatchNormv:
.LFB1981:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$6422528, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$120, %rsp
	.cfi_def_cfa_offset 176
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	call	_Znam@PLT
	movl	$6422528, %edi
	movq	%rax, %rbx
	call	_Znam@PLT
	movl	$256, %edi
	movq	%rax, %r15
	call	_Znam@PLT
	movl	$256, %edi
	movq	%rax, %r14
	call	_Znam@PLT
	movl	$256, %edi
	movq	%rax, %r12
	call	_Znam@PLT
	movl	$256, %edi
	movq	%rax, %rbp
	call	_Znam@PLT
	movl	$256, %edi
	movq	%rax, %r13
	call	_Znam@PLT
	movl	$256, %edi
	movq	%rax, 8(%rsp)
	call	_Znam@PLT
	xorl	%edx, %edx
	movq	%rax, 16(%rsp)
.L13:
	movq	%rdx, 24(%rsp)
	call	rand@PLT
	movq	24(%rsp), %rdx
	cvtsi2ssl	%eax, %xmm0
	mulss	.LC0(%rip), %xmm0
	movss	%xmm0, (%rbx,%rdx,4)
	incq	%rdx
	cmpq	$1605632, %rdx
	jne	.L13
	movss	.LC1(%rip), %xmm0
	xorl	%eax, %eax
.L14:
	movss	%xmm0, (%r14,%rax)
	movss	%xmm0, 0(%r13,%rax)
	addq	$4, %rax
	cmpq	$256, %rax
	jne	.L14
	xorl	%eax, %eax
	movl	$64, %ecx
	movq	%r12, %rdi
	movl	$6422528, %esi
	rep stosl
	movl	$64, %ecx
	movq	%rbp, %rdi
	rep stosl
	leaq	40(%rsp), %rdi
	call	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	leaq	48(%rsp), %rdi
	movl	$6422528, %esi
	call	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	leaq	56(%rsp), %rdi
	movl	$256, %esi
	call	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	leaq	64(%rsp), %rdi
	movl	$256, %esi
	call	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	leaq	72(%rsp), %rdi
	movl	$256, %esi
	call	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	leaq	80(%rsp), %rdi
	movl	$256, %esi
	call	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	leaq	88(%rsp), %rdi
	movl	$256, %esi
	call	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	leaq	96(%rsp), %rdi
	movl	$256, %esi
	call	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	movq	40(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$6422528, %edx
	call	cudaMemcpy@PLT
	movq	56(%rsp), %rdi
	movl	$1, %ecx
	movq	%r14, %rsi
	movl	$256, %edx
	call	cudaMemcpy@PLT
	movq	64(%rsp), %rdi
	movl	$1, %ecx
	movq	%r12, %rsi
	movl	$256, %edx
	call	cudaMemcpy@PLT
	movq	72(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$256, %edx
	call	cudaMemcpy@PLT
	movq	80(%rsp), %rdi
	movl	$1, %ecx
	movq	%r13, %rsi
	movl	$256, %edx
	call	cudaMemcpy@PLT
	pushq	$0
	.cfi_def_cfa_offset 184
	movss	.LC2(%rip), %xmm1
	pushq	$1
	.cfi_def_cfa_offset 192
	movss	.LC3(%rip), %xmm0
	pushq	$28
	.cfi_def_cfa_offset 200
	pushq	$28
	.cfi_def_cfa_offset 208
	pushq	$64
	.cfi_def_cfa_offset 216
	pushq	$32
	.cfi_def_cfa_offset 224
	pushq	144(%rsp)
	.cfi_def_cfa_offset 232
	pushq	144(%rsp)
	.cfi_def_cfa_offset 240
	movq	144(%rsp), %r9
	movq	136(%rsp), %r8
	movq	128(%rsp), %rcx
	movq	120(%rsp), %rdx
	movq	104(%rsp), %rdi
	movq	112(%rsp), %rsi
	call	_Z16batchNormForwardPfS_S_S_S_S_S_S_iiiiffbP11CUstream_st
	movq	112(%rsp), %rsi
	addq	$64, %rsp
	.cfi_def_cfa_offset 176
	movq	%r15, %rdi
	movl	$2, %ecx
	movl	$6422528, %edx
	call	cudaMemcpy@PLT
	movq	88(%rsp), %rsi
	movq	8(%rsp), %rdi
	movl	$2, %ecx
	movl	$256, %edx
	call	cudaMemcpy@PLT
	movq	96(%rsp), %rsi
	movq	16(%rsp), %rdi
	movl	$2, %ecx
	movl	$256, %edx
	call	cudaMemcpy@PLT
	leaq	.LC4(%rip), %rsi
	movl	$1, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	.LC5(%rip), %rsi
	movl	$1, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	xorl	%edx, %edx
	leaq	.LC6(%rip), %rcx
.L15:
	movq	%rcx, %rsi
	movl	$1, %edi
	movb	$1, %al
	movq	%rdx, 24(%rsp)
	cvtss2sd	(%r15,%rdx,4), %xmm0
	call	__printf_chk@PLT
	movq	24(%rsp), %rdx
	leaq	.LC6(%rip), %rcx
	incq	%rdx
	cmpq	$5, %rdx
	jne	.L15
	leaq	.LC7(%rip), %rsi
	movl	$1, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	%rbx, %rdi
	call	_ZdaPv@PLT
	movq	%r15, %rdi
	call	_ZdaPv@PLT
	movq	%r14, %rdi
	call	_ZdaPv@PLT
	movq	%r12, %rdi
	call	_ZdaPv@PLT
	movq	%rbp, %rdi
	call	_ZdaPv@PLT
	movq	%r13, %rdi
	call	_ZdaPv@PLT
	movq	8(%rsp), %rdi
	call	_ZdaPv@PLT
	movq	16(%rsp), %rdi
	call	_ZdaPv@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	48(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	movq	64(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rdi
	call	cudaFree@PLT
	movq	80(%rsp), %rdi
	call	cudaFree@PLT
	movq	88(%rsp), %rdi
	call	cudaFree@PLT
	movq	96(%rsp), %rdi
	call	cudaFree@PLT
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L16
	call	__stack_chk_fail@PLT
.L16:
	addq	$120, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE1981:
	.size	_Z13testBatchNormv, .-_Z13testBatchNormv
	.section	.rodata.str1.1
.LC8:
	.string	"Batch normalization test completed successfully!\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB1982:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	xorl	%edi, %edi
	call	cudaFree@PLT
	call	_Z13testBatchNormv
	leaq	.LC8(%rip), %rsi
	movl	$1, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	xorl	%eax, %eax
	popq	%rdx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE1982:
	.size	main, .-main
	.text
	.globl	_Z62__device_stub__Z23batchNormBackwardKernelPfS_S_S_S_S_S_S_iiiifPfS_S_S_S_S_S_S_iiiif
	.type	_Z62__device_stub__Z23batchNormBackwardKernelPfS_S_S_S_S_S_S_iiiifPfS_S_S_S_S_S_S_iiiif, @function
_Z62__device_stub__Z23batchNormBackwardKernelPfS_S_S_S_S_S_S_iiiifPfS_S_S_S_S_S_S_iiiif:
.LFB2009:
	.cfi_startproc
	endbr64
	subq	$264, %rsp
	.cfi_def_cfa_offset 272
	movq	272(%rsp), %rax
	movq	%rdi, 72(%rsp)
	leaq	96(%rsp), %rdi
	movq	%rsi, 64(%rsp)
	leaq	108(%rsp), %rsi
	movq	%rax, 24(%rsp)
	movq	280(%rsp), %rax
	movq	%rdx, 56(%rsp)
	leaq	80(%rsp), %rdx
	movq	%rcx, 48(%rsp)
	leaq	88(%rsp), %rcx
	movq	%r8, 40(%rsp)
	movq	%r9, 32(%rsp)
	movq	%rax, 16(%rsp)
	movss	%xmm0, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 248(%rsp)
	xorl	%eax, %eax
	leaq	72(%rsp), %rax
	movl	$1, 104(%rsp)
	movq	%rax, 144(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	288(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	296(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	304(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	312(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 240(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 96(%rsp)
	movq	%rax, 108(%rsp)
	movl	$1, 116(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L23
	pushq	88(%rsp)
	.cfi_def_cfa_offset 280
	leaq	_Z23batchNormBackwardKernelPfS_S_S_S_S_S_S_iiiif(%rip), %rdi
	pushq	88(%rsp)
	.cfi_def_cfa_offset 288
	movq	124(%rsp), %rcx
	movl	132(%rsp), %r8d
	movq	112(%rsp), %rsi
	movl	120(%rsp), %edx
	leaq	160(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 280
	popq	%rdx
	.cfi_def_cfa_offset 272
.L23:
	movq	248(%rsp), %rax
	subq	%fs:40, %rax
	je	.L25
	call	__stack_chk_fail@PLT
.L25:
	addq	$264, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2009:
	.size	_Z62__device_stub__Z23batchNormBackwardKernelPfS_S_S_S_S_S_S_iiiifPfS_S_S_S_S_S_S_iiiif, .-_Z62__device_stub__Z23batchNormBackwardKernelPfS_S_S_S_S_S_S_iiiifPfS_S_S_S_S_S_S_iiiif
	.globl	_Z23batchNormBackwardKernelPfS_S_S_S_S_S_S_iiiif
	.type	_Z23batchNormBackwardKernelPfS_S_S_S_S_S_S_iiiif, @function
_Z23batchNormBackwardKernelPfS_S_S_S_S_S_S_iiiif:
.LFB2010:
	.cfi_startproc
	endbr64
	jmp	_Z62__device_stub__Z23batchNormBackwardKernelPfS_S_S_S_S_S_S_iiiifPfS_S_S_S_S_S_S_iiiif
	.cfi_endproc
.LFE2010:
	.size	_Z23batchNormBackwardKernelPfS_S_S_S_S_S_S_iiiif, .-_Z23batchNormBackwardKernelPfS_S_S_S_S_S_S_iiiif
	.globl	_Z17batchNormBackwardPfS_S_S_S_S_S_S_iiiifP11CUstream_st
	.type	_Z17batchNormBackwardPfS_S_S_S_S_S_S_iiiifP11CUstream_st, @function
_Z17batchNormBackwardPfS_S_S_S_S_S_S_iiiifP11CUstream_st:
.LFB1980:
	.cfi_startproc
	endbr64
	movabsq	$4294967297, %rax
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%r9, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%r8, %rbx
	xorl	%r8d, %r8d
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movl	168(%rsp), %r12d
	movq	%rax, 60(%rsp)
	movl	176(%rsp), %r10d
	movl	184(%rsp), %r11d
	movq	%rdi, (%rsp)
	movq	%rsi, 8(%rsp)
	movq	192(%rsp), %r9
	movq	%rdx, 16(%rsp)
	movl	64(%rsp), %esi
	movl	$16777217, %edx
	movl	%r12d, 56(%rsp)
	movq	56(%rsp), %rdi
	salq	$8, %rdx
	movq	%rcx, 24(%rsp)
	movl	$1, %ecx
	movq	144(%rsp), %r13
	movl	%r10d, 44(%rsp)
	movq	152(%rsp), %r14
	movl	%r11d, 40(%rsp)
	movl	160(%rsp), %r15d
	movss	%xmm0, 36(%rsp)
	call	__cudaPushCallConfiguration@PLT
	movss	36(%rsp), %xmm0
	movl	40(%rsp), %r11d
	testl	%eax, %eax
	movl	44(%rsp), %r10d
	jne	.L28
	movl	%r12d, 168(%rsp)
	movq	24(%rsp), %rcx
	movq	%rbp, %r9
	movq	%rbx, %r8
	movl	%r15d, 160(%rsp)
	movq	16(%rsp), %rdx
	movq	%r14, 152(%rsp)
	movq	8(%rsp), %rsi
	movq	%r13, 144(%rsp)
	movq	(%rsp), %rdi
	movl	%r11d, 184(%rsp)
	movl	%r10d, 176(%rsp)
	addq	$88, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z62__device_stub__Z23batchNormBackwardKernelPfS_S_S_S_S_S_S_iiiifPfS_S_S_S_S_S_S_iiiif
.L28:
	.cfi_restore_state
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE1980:
	.size	_Z17batchNormBackwardPfS_S_S_S_S_S_S_iiiifP11CUstream_st, .-_Z17batchNormBackwardPfS_S_S_S_S_S_S_iiiifP11CUstream_st
	.section	.rodata.str1.1
.LC9:
	.string	"_Z23batchNormBackwardKernelPfS_S_S_S_S_S_S_iiiif"
.LC10:
	.string	"_Z22batchNormForwardKernelPfS_S_S_S_S_S_S_iiiiffb"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2012:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC9(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbp
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z23batchNormBackwardKernelPfS_S_S_S_S_S_S_iiiif(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbp, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC10(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z22batchNormForwardKernelPfS_S_S_S_S_S_S_iiiiffb(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2012:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC0:
	.long	805306368
	.align 4
.LC1:
	.long	1065353216
	.align 4
.LC2:
	.long	1036831949
	.align 4
.LC3:
	.long	925353388
	.ident	"GCC: (Ubuntu 11.4.0-1ubuntu1~22.04) 11.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>

// HIP kernel for batch normalization forward pass
__global__ void batchNormForwardKernel(
    float* input,             // Input data [N,C,H,W]
    float* output,            // Output data [N,C,H,W]
    float* gamma,             // Scale parameter [C]
    float* beta,              // Shift parameter [C]
    float* running_mean,      // Running mean [C]
    float* running_var,       // Running variance [C]
    float* batch_mean,        // Batch mean [C]
    float* batch_var,         // Batch variance [C]
    int N, int C, int H, int W,
    float epsilon,            // Small constant for numerical stability
    float momentum,           // Momentum for running averages
    bool training             // Whether in training mode
) {
    // Get channel index
    const int c = hipBlockIdx_x;
    
    if (c >= C) return;
    
    // Each thread block handles one channel
    const int thread_id = hipThreadIdx_x;
    const int block_size = hipBlockDim_x;
    
    const int spatial_size = H * W;
    const int feature_map_size = N * spatial_size;
    
    // Pointer to the start of this channel's data
    const float* channel_input = input + c * spatial_size;
    float* channel_output = output + c * spatial_size;
    
    // Compute mean and variance for this channel (training mode only)
    if (training) {
        float sum = 0.0f;
        float sq_sum = 0.0f;
        
        // Parallel reduction for mean computation
        for (int i = thread_id; i < feature_map_size; i += block_size) {
            int n = i / spatial_size;
            int hw = i % spatial_size;
            float val = channel_input[n * C * spatial_size + hw];
            sum += val;
            sq_sum += val * val;
        }
        
        // Warp-level reduction
        for (int stride = block_size / 2; stride > 0; stride >>= 1) {
            sum += __shfl_down(sum, stride);
            sq_sum += __shfl_down(sq_sum, stride);
        }
        
        // First thread in the block writes the result
        if (thread_id == 0) {
            float mean = sum / feature_map_size;
            float variance = (sq_sum / feature_map_size) - (mean * mean);
            
            batch_mean[c] = mean;
            batch_var[c] = variance;
            
            // Update running stats
            running_mean[c] = momentum * running_mean[c] + (1.0f - momentum) * mean;
            running_var[c] = momentum * running_var[c] + (1.0f - momentum) * variance;
        }
    }
    
    // Make sure batch stats are available to all threads
    __syncthreads();
    
    // Apply normalization
    for (int i = thread_id; i < feature_map_size; i += block_size) {
        int n = i / spatial_size;
        int hw = i % spatial_size;
        int idx = n * C * spatial_size + c * spatial_size + hw;
        
        float mean_val = training ? batch_mean[c] : running_mean[c];
        float var_val = training ? batch_var[c] : running_var[c];
        
        float normalized = (input[idx] - mean_val) / sqrtf(var_val + epsilon);
        output[idx] = gamma[c] * normalized + beta[c];
    }
}

// Host function to launch the batch normalization kernel
void batchNormForward(
    float* d_input,
    float* d_output,
    float* d_gamma,
    float* d_beta,
    float* d_running_mean,
    float* d_running_var,
    float* d_batch_mean,
    float* d_batch_var,
    int N, int C, int H, int W,
    float epsilon,
    float momentum,
    bool training,
    hipStream_t stream = 0
) {
    // Configure kernel launch parameters
    dim3 blocks(C);
    int threadsPerBlock = 256;  // Can be tuned for better performance
    
    hipLaunchKernelGGL(
        batchNormForwardKernel,
        blocks,
        threadsPerBlock,
        0,
        stream,
        d_input, d_output, d_gamma, d_beta,
        d_running_mean, d_running_var,
        d_batch_mean, d_batch_var,
        N, C, H, W, epsilon, momentum, training
    );
}

// Additional backward pass kernel for training
__global__ void batchNormBackwardKernel(
    float* input,             // Input data [N,C,H,W]
    float* d_output,          // Gradient w.r.t output [N,C,H,W]
    float* d_input,           // Gradient w.r.t input [N,C,H,W]
    float* gamma,             // Scale parameter [C]
    float* d_gamma,           // Gradient w.r.t gamma [C]
    float* d_beta,            // Gradient w.r.t beta [C]
    float* batch_mean,        // Batch mean [C]
    float* batch_var,         // Batch variance [C]
    int N, int C, int H, int W,
    float epsilon             // Small constant for numerical stability
) {
    // Get channel index
    const int c = hipBlockIdx_x;
    
    if (c >= C) return;
    
    // Each thread block handles one channel
    const int thread_id = hipThreadIdx_x;
    const int block_size = hipBlockDim_x;
    
    const int spatial_size = H * W;
    const int feature_map_size = N * spatial_size;
    
    // Calculate intermediate sums for backprop
    float sum_dy = 0.0f;
    float sum_dy_x = 0.0f;
    
    for (int i = thread_id; i < feature_map_size; i += block_size) {
        int n = i / spatial_size;
        int hw = i % spatial_size;
        int idx = n * C * spatial_size + c * spatial_size + hw;
        
        float dy = d_output[idx];
        float x = (input[idx] - batch_mean[c]) / sqrtf(batch_var[c] + epsilon);
        
        sum_dy += dy;
        sum_dy_x += dy * x;
    }
    
    // Warp-level reduction
    for (int stride = block_size / 2; stride > 0; stride >>= 1) {
        sum_dy += __shfl_down(sum_dy, stride);
        sum_dy_x += __shfl_down(sum_dy_x, stride);
    }
    
    // First thread in the block updates gradients for gamma and beta
    if (thread_id == 0) {
        d_beta[c] = sum_dy;
        d_gamma[c] = sum_dy_x;
    }
    
    __syncthreads();
    
    // Calculate gradients with respect to input
    float inv_std = 1.0f / sqrtf(batch_var[c] + epsilon);
    float N_inv = 1.0f / feature_map_size;
    
    for (int i = thread_id; i < feature_map_size; i += block_size) {
        int n = i / spatial_size;
        int hw = i % spatial_size;
        int idx = n * C * spatial_size + c * spatial_size + hw;
        
        float dy = d_output[idx];
        float x = input[idx] - batch_mean[c];
        
        // Apply chain rule for the backward pass
        d_input[idx] = gamma[c] * inv_std * (dy - (sum_dy + x * inv_std * sum_dy_x) * N_inv);
    }
}

// Host function to launch the batch normalization backward kernel
void batchNormBackward(
    float* d_input,
    float* d_output,
    float* d_d_input,
    float* d_gamma,
    float* d_d_gamma,
    float* d_d_beta,
    float* d_batch_mean,
    float* d_batch_var,
    int N, int C, int H, int W,
    float epsilon,
    hipStream_t stream = 0
) {
    // Configure kernel launch parameters
    dim3 blocks(C);
    int threadsPerBlock = 256;  // Can be tuned for better performance
    
    hipLaunchKernelGGL(
        batchNormBackwardKernel,
        blocks,
        threadsPerBlock,
        0,
        stream,
        d_input, d_output, d_d_input, d_gamma, d_d_gamma, d_d_beta,
        d_batch_mean, d_batch_var,
        N, C, H, W, epsilon
    );
}

// Simple test function to demonstrate usage
void testBatchNorm() {
    // Example dimensions
    const int N = 32;    // Batch size
    const int C = 64;    // Channels
    const int H = 28;    // Height
    const int W = 28;    // Width
    
    const int input_size = N * C * H * W;
    const int params_size = C;
    
    // Allocate host memory
    float* h_input = new float[input_size];
    float* h_output = new float[input_size];
    float* h_gamma = new float[params_size];
    float* h_beta = new float[params_size];
    float* h_running_mean = new float[params_size];
    float* h_running_var = new float[params_size];
    float* h_batch_mean = new float[params_size];
    float* h_batch_var = new float[params_size];
    
    // Initialize data (would normally come from your network)
    for (int i = 0; i < input_size; ++i) {
        h_input[i] = static_cast<float>(rand()) / RAND_MAX;
    }
    for (int i = 0; i < params_size; ++i) {
        h_gamma[i] = 1.0f;  // Initialize to 1
        h_beta[i] = 0.0f;   // Initialize to 0
        h_running_mean[i] = 0.0f;
        h_running_var[i] = 1.0f;
    }
    
    // Allocate device memory
    float *d_input, *d_output;
    float *d_gamma, *d_beta;
    float *d_running_mean, *d_running_var;
    float *d_batch_mean, *d_batch_var;
    
    hipMalloc(&d_input, input_size * sizeof(float));
    hipMalloc(&d_output, input_size * sizeof(float));
    hipMalloc(&d_gamma, params_size * sizeof(float));
    hipMalloc(&d_beta, params_size * sizeof(float));
    hipMalloc(&d_running_mean, params_size * sizeof(float));
    hipMalloc(&d_running_var, params_size * sizeof(float));
    hipMalloc(&d_batch_mean, params_size * sizeof(float));
    hipMalloc(&d_batch_var, params_size * sizeof(float));
    
    // Copy data to device
    hipMemcpy(d_input, h_input, input_size * sizeof(float), hipMemcpyHostToDevice);
    hipMemcpy(d_gamma, h_gamma, params_size * sizeof(float), hipMemcpyHostToDevice);
    hipMemcpy(d_beta, h_beta, params_size * sizeof(float), hipMemcpyHostToDevice);
    hipMemcpy(d_running_mean, h_running_mean, params_size * sizeof(float), hipMemcpyHostToDevice);
    hipMemcpy(d_running_var, h_running_var, params_size * sizeof(float), hipMemcpyHostToDevice);
    
    // Run batch normalization
    const float epsilon = 1e-5f;
    const float momentum = 0.1f;
    const bool training = true;
    
    batchNormForward(
        d_input, d_output, d_gamma, d_beta,
        d_running_mean, d_running_var,
        d_batch_mean, d_batch_var,
        N, C, H, W, epsilon, momentum, training
    );
    
    // Copy results back to host
    hipMemcpy(h_output, d_output, input_size * sizeof(float), hipMemcpyDeviceToHost);
    hipMemcpy(h_batch_mean, d_batch_mean, params_size * sizeof(float), hipMemcpyDeviceToHost);
    hipMemcpy(h_batch_var, d_batch_var, params_size * sizeof(float), hipMemcpyDeviceToHost);
    
    // Print some results for verification
    printf("Batch normalization completed\n");
    printf("First few values of the output:\n");
    for (int i = 0; i < 5; ++i) {
        printf("%f ", h_output[i]);
    }
    printf("\n");
    
    // Clean up
    delete[] h_input;
    delete[] h_output;
    delete[] h_gamma;
    delete[] h_beta;
    delete[] h_running_mean;
    delete[] h_running_var;
    delete[] h_batch_mean;
    delete[] h_batch_var;
    
    hipFree(d_input);
    hipFree(d_output);
    hipFree(d_gamma);
    hipFree(d_beta);
    hipFree(d_running_mean);
    hipFree(d_running_var);
    hipFree(d_batch_mean);
    hipFree(d_batch_var);
}

int main() {
    // Initialize HIP
    hipFree(0);  // Simple way to initialize the HIP runtime
    
    // Run the batch normalization test
    testBatchNorm();
    
    printf("Batch normalization test completed successfully!\n");
    return 0;
}
	.text
	.file	"20.cpp"
	.globl	_Z37__device_stub__batchNormForwardKernelPfS_S_S_S_S_S_S_iiiiffb # -- Begin function _Z37__device_stub__batchNormForwardKernelPfS_S_S_S_S_S_S_iiiiffb
	.p2align	4, 0x90
	.type	_Z37__device_stub__batchNormForwardKernelPfS_S_S_S_S_S_S_iiiiffb,@function
_Z37__device_stub__batchNormForwardKernelPfS_S_S_S_S_S_S_iiiiffb: # @_Z37__device_stub__batchNormForwardKernelPfS_S_S_S_S_S_S_iiiiffb
	.cfi_startproc
# %bb.0:
	subq	$232, %rsp
	.cfi_def_cfa_offset 240
	movzbl	288(%rsp), %eax
	movq	%rdi, 104(%rsp)
	movq	%rsi, 96(%rsp)
	movq	%rdx, 88(%rsp)
	movq	%rcx, 80(%rsp)
	movq	%r8, 72(%rsp)
	movq	%r9, 64(%rsp)
	movss	%xmm0, 12(%rsp)
	movss	%xmm1, 8(%rsp)
	movb	%al, 7(%rsp)
	leaq	104(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	96(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	88(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	240(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	248(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	256(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	264(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	272(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	280(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	7(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	48(%rsp), %rdi
	leaq	32(%rsp), %rsi
	leaq	24(%rsp), %rdx
	leaq	16(%rsp), %rcx
	callq	__hipPopCallConfiguration
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	movq	32(%rsp), %rcx
	movl	40(%rsp), %r8d
	leaq	112(%rsp), %r9
	movl	$_Z22batchNormForwardKernelPfS_S_S_S_S_S_S_iiiiffb, %edi
	pushq	16(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	32(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$248, %rsp
	.cfi_adjust_cfa_offset -248
	retq
.Lfunc_end0:
	.size	_Z37__device_stub__batchNormForwardKernelPfS_S_S_S_S_S_S_iiiiffb, .Lfunc_end0-_Z37__device_stub__batchNormForwardKernelPfS_S_S_S_S_S_S_iiiiffb
	.cfi_endproc
                                        # -- End function
	.globl	_Z16batchNormForwardPfS_S_S_S_S_S_S_iiiiffbP12ihipStream_t # -- Begin function _Z16batchNormForwardPfS_S_S_S_S_S_S_iiiiffbP12ihipStream_t
	.p2align	4, 0x90
	.type	_Z16batchNormForwardPfS_S_S_S_S_S_S_iiiiffbP12ihipStream_t,@function
_Z16batchNormForwardPfS_S_S_S_S_S_S_iiiiffbP12ihipStream_t: # @_Z16batchNormForwardPfS_S_S_S_S_S_S_iiiiffbP12ihipStream_t
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$280, %rsp                      # imm = 0x118
	.cfi_def_cfa_offset 336
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movss	%xmm1, 20(%rsp)                 # 4-byte Spill
	movss	%xmm0, 16(%rsp)                 # 4-byte Spill
	movq	%r9, %rbx
	movq	%r8, %r14
	movq	%rcx, %r15
	movq	%rdx, %r12
	movq	%rsi, %r13
	movq	%rdi, %rbp
	movl	360(%rsp), %eax
	movq	392(%rsp), %r9
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	leaq	(%rax,%rdx), %rdi
	orq	$256, %rdx                      # imm = 0x100
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_2
# %bb.1:
	movzbl	384(%rsp), %eax
	movl	376(%rsp), %ecx
	movl	368(%rsp), %edx
	movl	352(%rsp), %esi
	movq	344(%rsp), %rdi
	movq	336(%rsp), %r8
	movq	%rbp, 152(%rsp)
	movq	%r13, 144(%rsp)
	movq	%r12, 136(%rsp)
	movq	%r15, 128(%rsp)
	movq	%r14, 120(%rsp)
	movq	%rbx, 112(%rsp)
	movq	%r8, 104(%rsp)
	movq	%rdi, 96(%rsp)
	movl	%esi, 44(%rsp)
	movl	360(%rsp), %esi
	movl	%esi, 40(%rsp)
	movl	%edx, 36(%rsp)
	movl	%ecx, 32(%rsp)
	movss	16(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, 28(%rsp)
	movss	20(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, 24(%rsp)
	movb	%al, 15(%rsp)
	leaq	152(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	144(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	136(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	128(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	120(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	112(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	104(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	96(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	44(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 256(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 264(%rsp)
	leaq	15(%rsp), %rax
	movq	%rax, 272(%rsp)
	leaq	80(%rsp), %rdi
	leaq	64(%rsp), %rsi
	leaq	56(%rsp), %rdx
	leaq	48(%rsp), %rcx
	callq	__hipPopCallConfiguration
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	movq	64(%rsp), %rcx
	movl	72(%rsp), %r8d
	leaq	160(%rsp), %r9
	movl	$_Z22batchNormForwardKernelPfS_S_S_S_S_S_S_iiiiffb, %edi
	pushq	48(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	64(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
.LBB1_2:
	addq	$280, %rsp                      # imm = 0x118
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z16batchNormForwardPfS_S_S_S_S_S_S_iiiiffbP12ihipStream_t, .Lfunc_end1-_Z16batchNormForwardPfS_S_S_S_S_S_S_iiiiffbP12ihipStream_t
	.cfi_endproc
                                        # -- End function
	.globl	_Z38__device_stub__batchNormBackwardKernelPfS_S_S_S_S_S_S_iiiif # -- Begin function _Z38__device_stub__batchNormBackwardKernelPfS_S_S_S_S_S_S_iiiif
	.p2align	4, 0x90
	.type	_Z38__device_stub__batchNormBackwardKernelPfS_S_S_S_S_S_S_iiiif,@function
_Z38__device_stub__batchNormBackwardKernelPfS_S_S_S_S_S_S_iiiif: # @_Z38__device_stub__batchNormBackwardKernelPfS_S_S_S_S_S_S_iiiif
	.cfi_startproc
# %bb.0:
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	%rdi, 104(%rsp)
	movq	%rsi, 96(%rsp)
	movq	%rdx, 88(%rsp)
	movq	%rcx, 80(%rsp)
	movq	%r8, 72(%rsp)
	movq	%r9, 64(%rsp)
	movss	%xmm0, 12(%rsp)
	leaq	104(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	96(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	88(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	224(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	232(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	240(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	248(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	256(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	264(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	48(%rsp), %rdi
	leaq	32(%rsp), %rsi
	leaq	24(%rsp), %rdx
	leaq	16(%rsp), %rcx
	callq	__hipPopCallConfiguration
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	movq	32(%rsp), %rcx
	movl	40(%rsp), %r8d
	leaq	112(%rsp), %r9
	movl	$_Z23batchNormBackwardKernelPfS_S_S_S_S_S_S_iiiif, %edi
	pushq	16(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	32(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$232, %rsp
	.cfi_adjust_cfa_offset -232
	retq
.Lfunc_end2:
	.size	_Z38__device_stub__batchNormBackwardKernelPfS_S_S_S_S_S_S_iiiif, .Lfunc_end2-_Z38__device_stub__batchNormBackwardKernelPfS_S_S_S_S_S_S_iiiif
	.cfi_endproc
                                        # -- End function
	.globl	_Z17batchNormBackwardPfS_S_S_S_S_S_S_iiiifP12ihipStream_t # -- Begin function _Z17batchNormBackwardPfS_S_S_S_S_S_S_iiiifP12ihipStream_t
	.p2align	4, 0x90
	.type	_Z17batchNormBackwardPfS_S_S_S_S_S_S_iiiifP12ihipStream_t,@function
_Z17batchNormBackwardPfS_S_S_S_S_S_S_iiiifP12ihipStream_t: # @_Z17batchNormBackwardPfS_S_S_S_S_S_S_iiiifP12ihipStream_t
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$248, %rsp
	.cfi_def_cfa_offset 304
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movss	%xmm0, 8(%rsp)                  # 4-byte Spill
	movq	%r9, %rbx
	movq	%r8, %r14
	movq	%rcx, %r15
	movq	%rdx, %r12
	movq	%rsi, %r13
	movq	%rdi, %rbp
	movl	328(%rsp), %eax
	movq	352(%rsp), %r9
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	leaq	(%rax,%rdx), %rdi
	orq	$256, %rdx                      # imm = 0x100
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_2
# %bb.1:
	movl	344(%rsp), %eax
	movl	336(%rsp), %ecx
	movl	320(%rsp), %edx
	movq	312(%rsp), %rsi
	movq	304(%rsp), %rdi
	movq	%rbp, 136(%rsp)
	movq	%r13, 128(%rsp)
	movq	%r12, 120(%rsp)
	movq	%r15, 112(%rsp)
	movq	%r14, 104(%rsp)
	movq	%rbx, 96(%rsp)
	movq	%rdi, 88(%rsp)
	movq	%rsi, 80(%rsp)
	movl	%edx, 28(%rsp)
	movl	328(%rsp), %edx
	movl	%edx, 24(%rsp)
	movl	%ecx, 20(%rsp)
	movl	%eax, 16(%rsp)
	movss	8(%rsp), %xmm0                  # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, 12(%rsp)
	leaq	136(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	128(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	120(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	112(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	104(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	96(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	88(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	64(%rsp), %rdi
	leaq	48(%rsp), %rsi
	leaq	40(%rsp), %rdx
	leaq	32(%rsp), %rcx
	callq	__hipPopCallConfiguration
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	movq	48(%rsp), %rcx
	movl	56(%rsp), %r8d
	leaq	144(%rsp), %r9
	movl	$_Z23batchNormBackwardKernelPfS_S_S_S_S_S_S_iiiif, %edi
	pushq	32(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	48(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
.LBB3_2:
	addq	$248, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z17batchNormBackwardPfS_S_S_S_S_S_S_iiiifP12ihipStream_t, .Lfunc_end3-_Z17batchNormBackwardPfS_S_S_S_S_S_S_iiiifP12ihipStream_t
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _Z13testBatchNormv
.LCPI4_0:
	.long	0x30000000                      # float 4.65661287E-10
.LCPI4_1:
	.long	0x3727c5ac                      # float 9.99999974E-6
.LCPI4_2:
	.long	0x3dcccccd                      # float 0.100000001
	.text
	.globl	_Z13testBatchNormv
	.p2align	4, 0x90
	.type	_Z13testBatchNormv,@function
_Z13testBatchNormv:                     # @_Z13testBatchNormv
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$6422528, %edi                  # imm = 0x620000
	callq	_Znam
	movq	%rax, %rbx
	movl	$6422528, %edi                  # imm = 0x620000
	callq	_Znam
	movq	%rax, %r14
	movl	$256, %edi                      # imm = 0x100
	callq	_Znam
	movq	%rax, %r15
	movl	$256, %edi                      # imm = 0x100
	callq	_Znam
	movq	%rax, (%rsp)                    # 8-byte Spill
	movl	$256, %edi                      # imm = 0x100
	callq	_Znam
	movq	%rax, %r13
	movl	$256, %edi                      # imm = 0x100
	callq	_Znam
	movq	%rax, %rbp
	movl	$256, %edi                      # imm = 0x100
	callq	_Znam
	movq	%rax, 80(%rsp)                  # 8-byte Spill
	movl	$256, %edi                      # imm = 0x100
	callq	_Znam
	movq	%rax, 72(%rsp)                  # 8-byte Spill
	xorl	%r12d, %r12d
	.p2align	4, 0x90
.LBB4_1:                                # =>This Inner Loop Header: Depth=1
	callq	rand
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	mulss	.LCPI4_0(%rip), %xmm0
	movss	%xmm0, (%rbx,%r12,4)
	incq	%r12
	cmpq	$1605632, %r12                  # imm = 0x188000
	jne	.LBB4_1
# %bb.2:                                # %.preheader.preheader
	xorps	%xmm0, %xmm0
	movq	(%rsp), %rax                    # 8-byte Reload
	movups	%xmm0, 240(%rax)
	movups	%xmm0, 224(%rax)
	movups	%xmm0, 208(%rax)
	movups	%xmm0, 192(%rax)
	movups	%xmm0, 176(%rax)
	movups	%xmm0, 160(%rax)
	movups	%xmm0, 144(%rax)
	movups	%xmm0, 128(%rax)
	movups	%xmm0, 112(%rax)
	movups	%xmm0, 96(%rax)
	movups	%xmm0, 80(%rax)
	movups	%xmm0, 64(%rax)
	movups	%xmm0, 48(%rax)
	movups	%xmm0, 32(%rax)
	movups	%xmm0, 16(%rax)
	movups	%xmm0, (%rax)
	movups	%xmm0, 240(%r13)
	movups	%xmm0, 224(%r13)
	movups	%xmm0, 208(%r13)
	movups	%xmm0, 192(%r13)
	movups	%xmm0, 176(%r13)
	movups	%xmm0, 160(%r13)
	movups	%xmm0, 144(%r13)
	movups	%xmm0, 128(%r13)
	movups	%xmm0, 112(%r13)
	movups	%xmm0, 96(%r13)
	movups	%xmm0, 80(%r13)
	movups	%xmm0, 64(%r13)
	movups	%xmm0, 48(%r13)
	movups	%xmm0, 32(%r13)
	movups	%xmm0, 16(%r13)
	movups	%xmm0, (%r13)
	xorl	%eax, %eax
	.p2align	4, 0x90
.LBB4_3:                                # %.preheader
                                        # =>This Inner Loop Header: Depth=1
	movl	$1065353216, (%r15,%rax,4)      # imm = 0x3F800000
	movl	$1065353216, (%rbp,%rax,4)      # imm = 0x3F800000
	incq	%rax
	cmpq	$64, %rax
	jne	.LBB4_3
# %bb.4:
	leaq	64(%rsp), %rdi
	movl	$6422528, %esi                  # imm = 0x620000
	callq	hipMalloc
	leaq	56(%rsp), %rdi
	movl	$6422528, %esi                  # imm = 0x620000
	callq	hipMalloc
	leaq	48(%rsp), %rdi
	movl	$256, %esi                      # imm = 0x100
	callq	hipMalloc
	leaq	40(%rsp), %rdi
	movl	$256, %esi                      # imm = 0x100
	callq	hipMalloc
	leaq	32(%rsp), %rdi
	movl	$256, %esi                      # imm = 0x100
	callq	hipMalloc
	leaq	24(%rsp), %rdi
	movl	$256, %esi                      # imm = 0x100
	callq	hipMalloc
	leaq	16(%rsp), %rdi
	movl	$256, %esi                      # imm = 0x100
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movl	$256, %esi                      # imm = 0x100
	callq	hipMalloc
	movq	64(%rsp), %rdi
	movl	$6422528, %edx                  # imm = 0x620000
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	48(%rsp), %rdi
	movl	$256, %edx                      # imm = 0x100
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	40(%rsp), %rdi
	movl	$256, %edx                      # imm = 0x100
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	movq	32(%rsp), %rdi
	movl	$256, %edx                      # imm = 0x100
	movq	%r13, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	24(%rsp), %rdi
	movl	$256, %edx                      # imm = 0x100
	movq	%rbp, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	64(%rsp), %rdi
	movq	56(%rsp), %rsi
	movq	48(%rsp), %rdx
	movq	40(%rsp), %rcx
	movq	32(%rsp), %r8
	movq	24(%rsp), %r9
	movss	.LCPI4_1(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	movss	.LCPI4_2(%rip), %xmm1           # xmm1 = mem[0],zero,zero,zero
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	pushq	$28
	.cfi_adjust_cfa_offset 8
	pushq	$28
	.cfi_adjust_cfa_offset 8
	pushq	$64
	.cfi_adjust_cfa_offset 8
	pushq	$32
	.cfi_adjust_cfa_offset 8
	pushq	56(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	72(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z16batchNormForwardPfS_S_S_S_S_S_S_iiiiffbP12ihipStream_t
	addq	$64, %rsp
	.cfi_adjust_cfa_offset -64
	movq	56(%rsp), %rsi
	movl	$6422528, %edx                  # imm = 0x620000
	movq	%r14, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rsi
	movl	$256, %edx                      # imm = 0x100
	movq	80(%rsp), %rdi                  # 8-byte Reload
	movl	$2, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rsi
	movl	$256, %edx                      # imm = 0x100
	movq	72(%rsp), %rdi                  # 8-byte Reload
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$.Lstr, %edi
	callq	puts@PLT
	movl	$.Lstr.1, %edi
	callq	puts@PLT
	xorl	%r12d, %r12d
	.p2align	4, 0x90
.LBB4_5:                                # =>This Inner Loop Header: Depth=1
	movss	(%r14,%r12,4), %xmm0            # xmm0 = mem[0],zero,zero,zero
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str.2, %edi
	movb	$1, %al
	callq	printf
	incq	%r12
	cmpq	$5, %r12
	jne	.LBB4_5
# %bb.6:
	movl	$10, %edi
	callq	putchar@PLT
	movq	%rbx, %rdi
	callq	_ZdaPv
	movq	%r14, %rdi
	callq	_ZdaPv
	movq	%r15, %rdi
	callq	_ZdaPv
	movq	(%rsp), %rdi                    # 8-byte Reload
	callq	_ZdaPv
	movq	%r13, %rdi
	callq	_ZdaPv
	movq	%rbp, %rdi
	callq	_ZdaPv
	movq	80(%rsp), %rdi                  # 8-byte Reload
	callq	_ZdaPv
	movq	72(%rsp), %rdi                  # 8-byte Reload
	callq	_ZdaPv
	movq	64(%rsp), %rdi
	callq	hipFree
	movq	56(%rsp), %rdi
	callq	hipFree
	movq	48(%rsp), %rdi
	callq	hipFree
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z13testBatchNormv, .Lfunc_end4-_Z13testBatchNormv
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.p2align	4, 0x90
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rax
	.cfi_def_cfa_offset 16
	xorl	%edi, %edi
	callq	hipFree
	callq	_Z13testBatchNormv
	movl	$.Lstr.2, %edi
	callq	puts@PLT
	xorl	%eax, %eax
	popq	%rcx
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	main, .Lfunc_end5-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	cmpq	$0, __hip_gpubin_handle(%rip)
	jne	.LBB6_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB6_2:
	movq	__hip_gpubin_handle(%rip), %rbx
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z22batchNormForwardKernelPfS_S_S_S_S_S_S_iiiiffb, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z23batchNormBackwardKernelPfS_S_S_S_S_S_S_iiiif, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end6:
	.size	__hip_module_ctor, .Lfunc_end6-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB7_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB7_2:
	retq
.Lfunc_end7:
	.size	__hip_module_dtor, .Lfunc_end7-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z22batchNormForwardKernelPfS_S_S_S_S_S_S_iiiiffb,@object # @_Z22batchNormForwardKernelPfS_S_S_S_S_S_S_iiiiffb
	.section	.rodata,"a",@progbits
	.globl	_Z22batchNormForwardKernelPfS_S_S_S_S_S_S_iiiiffb
	.p2align	3, 0x0
_Z22batchNormForwardKernelPfS_S_S_S_S_S_S_iiiiffb:
	.quad	_Z37__device_stub__batchNormForwardKernelPfS_S_S_S_S_S_S_iiiiffb
	.size	_Z22batchNormForwardKernelPfS_S_S_S_S_S_S_iiiiffb, 8

	.type	_Z23batchNormBackwardKernelPfS_S_S_S_S_S_S_iiiif,@object # @_Z23batchNormBackwardKernelPfS_S_S_S_S_S_S_iiiif
	.globl	_Z23batchNormBackwardKernelPfS_S_S_S_S_S_S_iiiif
	.p2align	3, 0x0
_Z23batchNormBackwardKernelPfS_S_S_S_S_S_S_iiiif:
	.quad	_Z38__device_stub__batchNormBackwardKernelPfS_S_S_S_S_S_S_iiiif
	.size	_Z23batchNormBackwardKernelPfS_S_S_S_S_S_S_iiiif, 8

	.type	.L.str.2,@object                # @.str.2
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.2:
	.asciz	"%f "
	.size	.L.str.2, 4

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z22batchNormForwardKernelPfS_S_S_S_S_S_S_iiiiffb"
	.size	.L__unnamed_1, 50

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z23batchNormBackwardKernelPfS_S_S_S_S_S_S_iiiif"
	.size	.L__unnamed_2, 49

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"Batch normalization completed"
	.size	.Lstr, 30

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"First few values of the output:"
	.size	.Lstr.1, 32

	.type	.Lstr.2,@object                 # @str.2
.Lstr.2:
	.asciz	"Batch normalization test completed successfully!"
	.size	.Lstr.2, 49

	.section	".linker-options","e",@llvm_linker_options
	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z37__device_stub__batchNormForwardKernelPfS_S_S_S_S_S_S_iiiiffb
	.addrsig_sym _Z38__device_stub__batchNormBackwardKernelPfS_S_S_S_S_S_S_iiiif
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z22batchNormForwardKernelPfS_S_S_S_S_S_S_iiiiffb
	.addrsig_sym _Z23batchNormBackwardKernelPfS_S_S_S_S_S_S_iiiif
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z22batchNormForwardKernelPfS_S_S_S_S_S_S_iiiiffb ; -- Begin function _Z22batchNormForwardKernelPfS_S_S_S_S_S_S_iiiiffb
	.globl	_Z22batchNormForwardKernelPfS_S_S_S_S_S_S_iiiiffb
	.p2align	8
	.type	_Z22batchNormForwardKernelPfS_S_S_S_S_S_S_iiiiffb,@function
_Z22batchNormForwardKernelPfS_S_S_S_S_S_S_iiiiffb: ; @_Z22batchNormForwardKernelPfS_S_S_S_S_S_S_iiiiffb
; %bb.0:
	s_load_b32 s20, s[0:1], 0x44
	s_waitcnt lgkmcnt(0)
	s_cmp_ge_i32 s15, s20
	s_cbranch_scc1 .LBB0_15
; %bb.1:
	s_clause 0x5
	s_load_b64 s[2:3], s[0:1], 0x48
	s_load_b32 s12, s[0:1], 0x58
	s_load_b32 s13, s[0:1], 0x40
	s_load_b32 s14, s[0:1], 0x6c
	s_load_b64 s[18:19], s[0:1], 0x0
	s_load_b256 s[4:11], s[0:1], 0x20
	s_mov_b32 s16, s15
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s21, s3, s2
	s_bitcmp1_b32 s12, 0
	s_mul_i32 s22, s21, s13
	s_cselect_b32 s24, -1, 0
	v_cmp_gt_i32_e32 vcc_lo, s22, v0
	s_and_b32 s23, s14, 0xffff
	s_bitcmp0_b32 s12, 0
	s_cbranch_scc1 .LBB0_12
; %bb.2:                                ; %.preheader122
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 0
	s_mov_b32 s3, 0
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB0_6
; %bb.3:                                ; %.lr.ph
	s_mul_i32 s12, s21, s16
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s13, s12, 31
	s_lshl_b64 s[12:13], s[12:13], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_add_u32 s12, s18, s12
	s_addc_u32 s13, s19, s13
	s_ashr_i32 s14, s21, 31
	s_add_i32 s15, s21, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s15, s15, s14
	v_cvt_f32_u32_e32 v1, s15
	s_sub_i32 s17, 0, s15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v2, s17, v1
	s_mul_i32 s17, s21, s20
	s_sub_i32 s17, s17, s21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v4, v1, v2
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 0
	v_dual_mov_b32 v1, v0 :: v_dual_add_nc_u32 v4, v1, v4
	.p2align	6
.LBB0_4:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v5, v1, v4
	v_mul_lo_u32 v6, v5, s15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v6, v1, v6
	v_subrev_nc_u32_e32 v8, s15, v6
	v_cmp_le_u32_e32 vcc_lo, s15, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v6, v6, v8 :: v_dual_add_nc_u32 v7, 1, v5
	v_cndmask_b32_e32 v5, v5, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s15, v6
	v_add_nc_u32_e32 v7, 1, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v5, v5, v7, vcc_lo
	v_xor_b32_e32 v5, s14, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_subrev_nc_u32_e32 v7, s14, v5
	v_mad_u64_u32 v[5:6], null, v7, s17, v[1:2]
	v_add_nc_u32_e32 v1, s23, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s12, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s13, v6, vcc_lo
	v_cmp_le_i32_e32 vcc_lo, s22, v1
	global_load_b32 v5, v[5:6], off
	s_or_b32 s3, vcc_lo, s3
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v2, v2, v5
	v_fmac_f32_e32 v3, v5, v5
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB0_4
; %bb.5:                                ; %Flow185
	s_or_b32 exec_lo, exec_lo, s3
.LBB0_6:                                ; %Flow186
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
	s_cmp_lt_u32 s23, 2
	s_cbranch_scc1 .LBB0_9
; %bb.7:                                ; %.lr.ph131
	v_mbcnt_lo_u32_b32 v1, -1, 0
	s_mov_b32 s2, s23
.LBB0_8:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_lshr_b32 s3, s2, 1
	s_cmp_lt_u32 s2, 4
	v_add_nc_u32_e32 v4, s3, v1
	s_mov_b32 s2, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, 32, v4
	v_cndmask_b32_e64 v4, 0, s3, vcc_lo
	v_add_lshl_u32 v4, v4, v1, 2
	ds_bpermute_b32 v5, v4, v2
	ds_bpermute_b32 v4, v4, v3
	s_waitcnt lgkmcnt(0)
	v_dual_add_f32 v2, v2, v5 :: v_dual_add_f32 v3, v3, v4
	s_cbranch_scc0 .LBB0_8
.LBB0_9:                                ; %Flow184
	s_mov_b32 s3, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB0_11
; %bb.10:
	v_cvt_f32_i32_e32 v1, s22
	s_ashr_i32 s17, s16, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[12:13], s[16:17], 2
	s_add_u32 s14, s8, s12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_div_scale_f32 v4, null, v1, v1, v2
	v_div_scale_f32 v5, null, v1, v1, v3
	v_div_scale_f32 v10, vcc_lo, v2, v1, v2
	v_rcp_f32_e32 v6, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_rcp_f32_e32 v7, v5
	s_addc_u32 s15, s9, s13
	s_add_u32 s26, s10, s12
	s_addc_u32 s27, s11, s13
	s_add_u32 s28, s4, s12
	s_addc_u32 s29, s5, s13
	s_add_u32 s12, s6, s12
	s_addc_u32 s13, s7, s13
	s_waitcnt_depctr 0xfff
	v_fma_f32 v8, -v4, v6, 1.0
	v_fma_f32 v9, -v5, v7, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v6, v8, v6 :: v_dual_fmac_f32 v7, v9, v7
	v_div_scale_f32 v8, s2, v3, v1, v3
	v_mul_f32_e32 v9, v10, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v12, -v4, v9, v10
	v_fmac_f32_e32 v9, v12, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v4, -v4, v9, v10
	v_div_fmas_f32 v4, v4, v6, v9
	s_mov_b32 vcc_lo, s2
	s_load_b32 s2, s[0:1], 0x54
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v2, v4, v1, v2
	v_mul_f32_e32 v11, v8, v7
	v_fma_f32 v13, -v5, v11, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v11, v13, v7
	v_fma_f32 v5, -v5, v11, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v5, v5, v7, v11
	v_div_fixup_f32 v1, v5, v1, v3
	v_mov_b32_e32 v3, 0
	s_waitcnt lgkmcnt(0)
	v_sub_f32_e64 v5, 1.0, s2
	s_delay_alu instid0(VALU_DEP_3)
	v_fma_f32 v1, -v2, v2, v1
	s_clause 0x1
	global_store_b32 v3, v2, s[14:15]
	global_store_b32 v3, v1, s[26:27]
	global_load_b32 v4, v3, s[28:29]
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v4, s2, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, v5, v2
	global_store_b32 v3, v4, s[28:29]
	global_load_b32 v2, v3, s[12:13]
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v2, s2, v2
	v_fmac_f32_e32 v2, v5, v1
	global_store_b32 v3, v2, s[12:13]
.LBB0_11:                               ; %Flow182
	s_or_b32 exec_lo, exec_lo, s3
.LBB0_12:
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s22, v0
	s_cbranch_execz .LBB0_15
; %bb.13:                               ; %.lr.ph136
	s_clause 0x1
	s_load_b128 s[12:15], s[0:1], 0x8
	s_load_b64 s[26:27], s[0:1], 0x18
	s_ashr_i32 s17, s16, 31
	s_and_b32 s2, s24, exec_lo
	s_cselect_b32 s3, s9, s5
	s_cselect_b32 s2, s8, s4
	s_lshl_b64 s[8:9], s[16:17], 2
	s_load_b32 s1, s[0:1], 0x50
	s_add_u32 s2, s2, s8
	s_addc_u32 s3, s3, s9
	s_and_b32 s4, s24, exec_lo
	s_cselect_b32 s4, s10, s6
	s_cselect_b32 s5, s11, s7
	s_add_u32 s4, s4, s8
	s_addc_u32 s5, s5, s9
	s_waitcnt lgkmcnt(0)
	s_add_u32 s6, s14, s8
	s_addc_u32 s7, s15, s9
	s_add_u32 s8, s26, s8
	s_addc_u32 s9, s27, s9
	s_ashr_i32 s10, s21, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s11, s21, s10
	s_xor_b32 s11, s11, s10
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v1, s11
	s_sub_i32 s14, 0, s11
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v1, v1
	v_mul_lo_u32 v2, s14, v1
	s_mov_b32 s14, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v2, v1, v2
	v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v1, v1, v2
.LBB0_14:                               ; =>This Inner Loop Header: Depth=1
	s_clause 0x1
	global_load_b32 v7, v2, s[2:3]
	global_load_b32 v8, v2, s[4:5]
	v_mul_hi_u32 v3, v0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v4, v3, s11
	v_sub_nc_u32_e32 v4, v0, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v6, s11, v4
	v_cmp_le_u32_e32 vcc_lo, s11, v4
	v_dual_cndmask_b32 v4, v4, v6 :: v_dual_add_nc_u32 v5, 1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v3, v3, v5, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s11, v4
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v8, s1, v8 :: v_dual_add_nc_u32 v5, 1, v3
	v_dual_mul_f32 v10, 0x4f800000, v8 :: v_dual_cndmask_b32 v3, v3, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v3, s10, v3
	v_subrev_nc_u32_e32 v5, s10, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[3:4], null, v5, s20, s[16:17]
	v_mul_lo_u32 v4, v5, s21
	v_mul_lo_u32 v3, v3, s21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v3, v4
	v_add_nc_u32_e32 v3, v0, v3
	v_add_nc_u32_e32 v0, s23, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s18, v3
	v_add_co_ci_u32_e32 v6, vcc_lo, s19, v4, vcc_lo
	global_load_b32 v5, v[5:6], off
	s_clause 0x1
	global_load_b32 v6, v2, s[6:7]
	global_load_b32 v9, v2, s[8:9]
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v8
	v_cndmask_b32_e32 v8, v8, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v10, v8
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v11, -1, v10
	v_add_nc_u32_e32 v12, 1, v10
	v_fma_f32 v13, -v11, v10, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cmp_ge_f32_e64 s0, 0, v13
	s_waitcnt vmcnt(2)
	v_sub_f32_e32 v5, v5, v7
	v_fma_f32 v14, -v12, v10, v8
	v_cndmask_b32_e64 v10, v10, v11, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e64 s0, 0, v14
	v_cndmask_b32_e64 v10, v10, v12, s0
	v_add_co_u32 v3, s0, s12, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v4, s0, s13, v4, s0
	v_mul_f32_e32 v11, 0x37800000, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v10, v10, v11, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v8, 0x260
	v_cndmask_b32_e32 v8, v10, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v7, null, v8, v8, v5
	v_div_scale_f32 v12, vcc_lo, v5, v8, v5
	v_rcp_f32_e32 v10, v7
	s_waitcnt_depctr 0xfff
	v_fma_f32 v11, -v7, v10, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v10, v11, v10
	v_mul_f32_e32 v11, v12, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v13, -v7, v11, v12
	v_fmac_f32_e32 v11, v13, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v7, -v7, v11, v12
	v_div_fmas_f32 v7, v7, v10, v11
	v_cmp_le_i32_e32 vcc_lo, s22, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v5, v7, v8, v5
	s_or_b32 s14, vcc_lo, s14
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v9, v6, v5
	global_store_b32 v[3:4], v9, off
	s_and_not1_b32 exec_lo, exec_lo, s14
	s_cbranch_execnz .LBB0_14
.LBB0_15:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z22batchNormForwardKernelPfS_S_S_S_S_S_S_iiiiffb
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 352
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 15
		.amdhsa_next_free_sgpr 30
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z22batchNormForwardKernelPfS_S_S_S_S_S_S_iiiiffb, .Lfunc_end0-_Z22batchNormForwardKernelPfS_S_S_S_S_S_S_iiiiffb
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1616
; NumSgprs: 32
; NumVgprs: 15
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 32
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z23batchNormBackwardKernelPfS_S_S_S_S_S_S_iiiif ; -- Begin function _Z23batchNormBackwardKernelPfS_S_S_S_S_S_S_iiiif
	.globl	_Z23batchNormBackwardKernelPfS_S_S_S_S_S_S_iiiif
	.p2align	8
	.type	_Z23batchNormBackwardKernelPfS_S_S_S_S_S_S_iiiif,@function
_Z23batchNormBackwardKernelPfS_S_S_S_S_S_S_iiiif: ; @_Z23batchNormBackwardKernelPfS_S_S_S_S_S_S_iiiif
; %bb.0:
	s_load_b32 s18, s[0:1], 0x44
	s_waitcnt lgkmcnt(0)
	s_cmp_ge_i32 s15, s18
	s_cbranch_scc1 .LBB1_13
; %bb.1:
	s_clause 0x5
	s_load_b64 s[12:13], s[0:1], 0x48
	s_load_b32 s2, s[0:1], 0x40
	s_load_b32 s14, s[0:1], 0x64
	s_load_b32 s3, s[0:1], 0x50
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b128 s[8:11], s[0:1], 0x30
	v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, 0
	s_mov_b32 s16, s15
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s19, s13, s12
	s_mov_b32 s13, 0
	s_mul_i32 s20, s19, s2
	s_and_b32 s21, s14, 0xffff
	s_mov_b32 s12, exec_lo
	v_cmpx_gt_i32_e64 s20, v0
	s_cbranch_execz .LBB1_5
; %bb.2:                                ; %.lr.ph
	s_ashr_i32 s17, s16, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[14:15], s[16:17], 2
	s_add_u32 s22, s8, s14
	s_addc_u32 s23, s9, s15
	s_add_u32 s14, s10, s14
	s_addc_u32 s15, s11, s15
	s_load_b32 s2, s[14:15], 0x0
	s_ashr_i32 s14, s19, 31
	s_waitcnt lgkmcnt(0)
	v_add_f32_e64 v1, s2, s3
	s_add_i32 s2, s19, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_xor_b32 s15, s2, s14
	v_mul_f32_e32 v2, 0x4f800000, v1
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v4, v1, v2, vcc_lo
	v_cvt_f32_u32_e32 v1, s15
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_sqrt_f32_e32 v2, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_cvt_u32_f32_e32 v7, v1
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v3, -1, v2
	v_add_nc_u32_e32 v5, 1, v2
	v_fma_f32 v6, -v3, v2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v1, -v5, v2, v4
	v_cmp_ge_f32_e64 s2, 0, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cndmask_b32_e64 v2, v2, v3, s2
	s_sub_i32 s2, 0, s15
	v_mul_lo_u32 v3, s2, v7
	v_cmp_lt_f32_e64 s2, 0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v1, v2, v5, s2
	s_load_b32 s2, s[22:23], 0x0
	v_mul_hi_u32 v3, v7, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v2, 0x37800000, v1
	v_dual_cndmask_b32 v5, v1, v2 :: v_dual_mov_b32 v2, 0
	v_cmp_class_f32_e64 vcc_lo, v4, 0x260
	v_mov_b32_e32 v1, 0
	s_delay_alu instid0(VALU_DEP_3)
	v_dual_cndmask_b32 v4, v5, v4 :: v_dual_add_nc_u32 v3, v7, v3
	v_mov_b32_e32 v5, v0
.LBB1_3:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v6, v5, v3
	v_mul_lo_u32 v7, v6, s15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v7, v5, v7
	v_subrev_nc_u32_e32 v9, s15, v7
	v_cmp_le_u32_e32 vcc_lo, s15, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v7, v7, v9 :: v_dual_add_nc_u32 v8, 1, v6
	v_cndmask_b32_e32 v6, v6, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s15, v7
	v_add_nc_u32_e32 v8, 1, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v6, v6, v8, vcc_lo
	v_xor_b32_e32 v6, s14, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_subrev_nc_u32_e32 v8, s14, v6
	v_mad_u64_u32 v[6:7], null, v8, s18, s[16:17]
	v_mul_lo_u32 v7, v8, s19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v6, v6, s19
	v_sub_nc_u32_e32 v6, v6, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v6, v5, v6
	v_add_nc_u32_e32 v5, s21, v5
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	v_add_co_u32 v8, vcc_lo, s4, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, s5, v7, vcc_lo
	v_add_co_u32 v6, vcc_lo, s6, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
	global_load_b32 v8, v[8:9], off
	global_load_b32 v6, v[6:7], off
	s_waitcnt vmcnt(1) lgkmcnt(0)
	v_subrev_f32_e32 v7, s2, v8
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v1, v1, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v8, null, v4, v4, v7
	v_div_scale_f32 v11, vcc_lo, v7, v4, v7
	v_rcp_f32_e32 v9, v8
	s_waitcnt_depctr 0xfff
	v_fma_f32 v10, -v8, v9, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v9, v10, v9
	v_mul_f32_e32 v10, v11, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v12, -v8, v10, v11
	v_fmac_f32_e32 v10, v12, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v8, -v8, v10, v11
	v_div_fmas_f32 v8, v8, v9, v10
	v_cmp_le_i32_e32 vcc_lo, s20, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v7, v8, v4, v7
	s_or_b32 s13, vcc_lo, s13
	v_fmac_f32_e32 v2, v6, v7
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB1_3
; %bb.4:                                ; %Flow163
	s_or_b32 exec_lo, exec_lo, s13
.LBB1_5:                                ; %Flow164
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s12
	s_cmp_lt_u32 s21, 2
	s_cbranch_scc1 .LBB1_8
; %bb.6:                                ; %.lr.ph111
	v_mbcnt_lo_u32_b32 v3, -1, 0
	s_mov_b32 s2, s21
.LBB1_7:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_lshr_b32 s12, s2, 1
	s_cmp_lt_u32 s2, 4
	v_add_nc_u32_e32 v4, s12, v3
	s_mov_b32 s2, s12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, 32, v4
	v_cndmask_b32_e64 v4, 0, s12, vcc_lo
	v_add_lshl_u32 v4, v4, v3, 2
	ds_bpermute_b32 v5, v4, v1
	ds_bpermute_b32 v4, v4, v2
	s_waitcnt lgkmcnt(0)
	v_dual_add_f32 v1, v1, v5 :: v_dual_add_f32 v2, v2, v4
	s_cbranch_scc0 .LBB1_7
.LBB1_8:                                ; %Flow162
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB1_10
; %bb.9:
	s_load_b128 s[12:15], s[0:1], 0x20
	s_ashr_i32 s17, s16, 31
	v_mov_b32_e32 v3, 0
	s_lshl_b64 s[22:23], s[16:17], 2
	s_waitcnt lgkmcnt(0)
	s_add_u32 s14, s14, s22
	s_addc_u32 s15, s15, s23
	s_add_u32 s12, s12, s22
	s_addc_u32 s13, s13, s23
	s_clause 0x1
	global_store_b32 v3, v1, s[14:15]
	global_store_b32 v3, v2, s[12:13]
.LBB1_10:
	s_or_b32 exec_lo, exec_lo, s2
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s20, v0
	s_cbranch_execz .LBB1_13
; %bb.11:                               ; %.lr.ph116
	s_ashr_i32 s17, s16, 31
	v_mov_b32_e32 v3, 0
	s_lshl_b64 s[22:23], s[16:17], 2
	s_load_b128 s[12:15], s[0:1], 0x10
	s_add_u32 s10, s10, s22
	s_addc_u32 s11, s11, s23
	global_load_b32 v4, v3, s[10:11]
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v4, s3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v5, 0x4f800000, v4
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v4
	v_cndmask_b32_e32 v4, v4, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v5, v4
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v6, -1, v5
	v_add_nc_u32_e32 v7, 1, v5
	v_fma_f32 v8, -v6, v5, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v9, -v7, v5, v4
	v_cmp_ge_f32_e64 s2, 0, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_f32_e64 s0, 0, v9
	v_cndmask_b32_e64 v5, v5, v6, s2
	s_add_u32 s2, s8, s22
	s_addc_u32 s3, s9, s23
	s_waitcnt lgkmcnt(0)
	s_add_u32 s8, s14, s22
	s_addc_u32 s9, s15, s23
	v_cndmask_b32_e64 v5, v5, v7, s0
	v_cvt_f32_i32_e32 v7, s20
	s_ashr_i32 s1, s19, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_add_i32 s0, s19, s1
	v_mul_f32_e32 v6, 0x37800000, v5
	s_xor_b32 s10, s0, s1
	v_div_scale_f32 v13, s0, 1.0, v7, 1.0
	v_cvt_f32_u32_e32 v10, s10
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v5, v5, v6, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v4, 0x260
	v_div_scale_f32 v6, null, v7, v7, 1.0
	v_rcp_iflag_f32_e32 v10, v10
	s_sub_i32 s11, 0, s10
	v_cndmask_b32_e32 v4, v5, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v8, v6
	v_div_scale_f32 v5, null, v4, v4, 1.0
	v_div_scale_f32 v14, vcc_lo, 1.0, v4, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v9, v5
	s_waitcnt_depctr 0xfff
	v_fma_f32 v11, -v6, v8, 1.0
	v_fmac_f32_e32 v8, v11, v8
	v_fma_f32 v12, -v5, v9, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v9, v12, v9 :: v_dual_mul_f32 v10, 0x4f7ffffe, v10
	v_mul_f32_e32 v11, v14, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_u32_f32_e32 v10, v10
	v_fma_f32 v15, -v5, v11, v14
	v_mul_f32_e32 v12, v13, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v17, s11, v10
	s_mov_b32 s11, 0
	v_fmac_f32_e32 v11, v15, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v16, -v6, v12, v13
	v_fma_f32 v5, -v5, v11, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v12, v16, v8
	v_div_fmas_f32 v5, v5, v9, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f32 v6, -v6, v12, v13
	v_mul_hi_u32 v13, v10, v17
	s_mov_b32 vcc_lo, s0
	v_div_fixup_f32 v4, v5, v4, 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v6, v6, v8, v12
	v_div_fixup_f32 v5, v6, v7, 1.0
	s_delay_alu instid0(VALU_DEP_4)
	v_add_nc_u32_e32 v6, v10, v13
.LBB1_12:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v7, v0, v6
	v_mul_lo_u32 v8, v7, s10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v8, v0, v8
	v_subrev_nc_u32_e32 v10, s10, v8
	v_cmp_le_u32_e32 vcc_lo, s10, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v8, v8, v10 :: v_dual_add_nc_u32 v9, 1, v7
	v_cndmask_b32_e32 v7, v7, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s10, v8
	v_add_nc_u32_e32 v9, 1, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v7, v7, v9, vcc_lo
	v_xor_b32_e32 v7, s1, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_subrev_nc_u32_e32 v9, s1, v7
	v_mad_u64_u32 v[7:8], null, v9, s18, s[16:17]
	v_mul_lo_u32 v8, v9, s19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v7, v7, s19
	v_sub_nc_u32_e32 v7, v7, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v7, v0, v7
	v_add_nc_u32_e32 v0, s21, v0
	v_ashrrev_i32_e32 v8, 31, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	v_add_co_u32 v9, vcc_lo, s4, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v10, vcc_lo, s5, v8, vcc_lo
	global_load_b32 v11, v3, s[2:3]
	global_load_b32 v12, v[9:10], off
	v_add_co_u32 v9, vcc_lo, s6, v7
	v_add_co_ci_u32_e32 v10, vcc_lo, s7, v8, vcc_lo
	global_load_b32 v13, v3, s[8:9]
	global_load_b32 v9, v[9:10], off
	v_cmp_le_i32_e32 vcc_lo, s20, v0
	v_add_co_u32 v7, s0, s12, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v8, s0, s13, v8, s0
	s_or_b32 s11, vcc_lo, s11
	s_waitcnt vmcnt(2)
	v_sub_f32_e32 v10, v12, v11
	v_mul_f32_e32 v10, v4, v10
	s_waitcnt vmcnt(1)
	v_mul_f32_e32 v11, v4, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f32 v10, v2, v10, v1
	s_waitcnt vmcnt(0)
	v_fma_f32 v9, -v5, v10, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v9, v11, v9
	global_store_b32 v[7:8], v9, off
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB1_12
.LBB1_13:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z23batchNormBackwardKernelPfS_S_S_S_S_S_S_iiiif
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 344
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 18
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z23batchNormBackwardKernelPfS_S_S_S_S_S_S_iiiif, .Lfunc_end1-_Z23batchNormBackwardKernelPfS_S_S_S_S_S_S_iiiif
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1700
; NumSgprs: 26
; NumVgprs: 18
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 18
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .offset:         64
        .size:           4
        .value_kind:     by_value
      - .offset:         68
        .size:           4
        .value_kind:     by_value
      - .offset:         72
        .size:           4
        .value_kind:     by_value
      - .offset:         76
        .size:           4
        .value_kind:     by_value
      - .offset:         80
        .size:           4
        .value_kind:     by_value
      - .offset:         84
        .size:           4
        .value_kind:     by_value
      - .offset:         88
        .size:           1
        .value_kind:     by_value
      - .offset:         96
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         100
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         104
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         108
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         110
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         112
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         114
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         116
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         118
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         136
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         144
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         152
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         160
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 352
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z22batchNormForwardKernelPfS_S_S_S_S_S_S_iiiiffb
    .private_segment_fixed_size: 0
    .sgpr_count:     32
    .sgpr_spill_count: 0
    .symbol:         _Z22batchNormForwardKernelPfS_S_S_S_S_S_S_iiiiffb.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     15
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .offset:         64
        .size:           4
        .value_kind:     by_value
      - .offset:         68
        .size:           4
        .value_kind:     by_value
      - .offset:         72
        .size:           4
        .value_kind:     by_value
      - .offset:         76
        .size:           4
        .value_kind:     by_value
      - .offset:         80
        .size:           4
        .value_kind:     by_value
      - .offset:         88
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         92
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         96
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         100
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         102
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         104
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         106
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         108
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         110
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         136
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         144
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         152
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 344
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z23batchNormBackwardKernelPfS_S_S_S_S_S_S_iiiif
    .private_segment_fixed_size: 0
    .sgpr_count:     26
    .sgpr_spill_count: 0
    .symbol:         _Z23batchNormBackwardKernelPfS_S_S_S_S_S_S_iiiif.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     18
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
