I. INTRODUCTION  
II. FPGA FOR DL ACCELERATION  
A. Key DL Acceleration Requirements  
B. FPGA Strengths for DL Acceleration  
C. FPGA-Based DL Inference Acceleration Styles  
D. Examples of DL Acceleration on FPGAs  
III. FPGA ARCHITECTURE & OPPORTUNITIES FOR DL  
A. Programmable Logic & Routing  
B. Digital Signal Processing Blocks  
C. On-Chip Block Memories  
D. Interposers  
E. Networks-on-Chip and Embedded Accelerators  
IV. FPGA ARCHITECTURE EXPLORATION  
A. Tools and Benchmarks  
B. Methodology  
C. Taxonomy of FPGA Architecture Enhancements for DL  
V. ENHANCING EXISTING FPGA FABRIC BLOCKS  
A. Logic Blocks  
B. DSPs  
C. BRAMs  
VI. IN-FABRIC TENSOR BLOCKS  
VII. BEYOND THE FPGA FABRIC  
A. Reconfigurable Acceleration Devices  
B. DL Chiplets  
VIII. SUMMARY